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61 lines
2.2 KiB
Verilog
61 lines
2.2 KiB
Verilog
/* ================================================================
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* VT52
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*
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* Copyright (C) 2024 Fred Van Eijk
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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* ================================================================
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*/
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/**
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* Keymap ROM (2KB, maps keycodes to ASCII chars)
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* This could be a RAM to allow keymap modifications, but not for now
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* There's 8 planes for each keycode (controlled by the highest three bits)
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* MSB is for long keycode vs short keycode, the the next two bits:
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* 00: no shift or caps lock
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* 01: just shift
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* 10: just caps lock
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* 11: caps lock & shift
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*/
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module keymap_rom
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(input clk,
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input [10:0] addr,
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output reg [7:0] dout
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);
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reg [7:0] mem [2047:0];
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integer i;
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initial begin
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// the hex file is sparse, prefill with zeros
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// XXX yosys doesn't like this, it overrides the readmemh
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// so for now just assume that all other positions have zeros...
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// for (i = 0; i < 2047; i = i + 1) mem[i] = "b";
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$readmemh("mem/keymap.hex", mem);
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end
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always @(posedge clk) begin
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dout <= mem[addr];
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end
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endmodule |