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https://github.com/MiSTer-devel/VT52_MiSTer.git
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93 lines
3.2 KiB
Verilog
93 lines
3.2 KiB
Verilog
/* ================================================================
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* VT52
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*
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* Copyright (C) 2024 Fred Van Eijk
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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* ================================================================
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*/
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module input_multiplexer
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(
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input clk,
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input reset,
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// Keyboard input interface
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input [7:0] kbd_data,
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input kbd_valid,
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output reg kbd_ready,
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// UART input interface
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input [7:0] uart_data,
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input uart_valid,
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output reg uart_ready,
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// Output interface to command handler
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output reg [7:0] out_data,
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output reg out_valid,
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output reg out_from_uart,
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input out_ready
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);
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// State machine with simplified ready logic
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always @(posedge clk) begin
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if (reset) begin
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out_data <= 8'h0;
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out_valid <= 1'b0;
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out_from_uart <= 1'b0;
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kbd_ready <= 1'b1;
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uart_ready <= 1'b1;
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end
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else begin
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// If command handler has accepted the data, clear valid
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if (out_valid && out_ready) begin
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out_valid <= 1'b0;
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kbd_ready <= 1'b1;
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uart_ready <= 1'b1;
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end
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// If we're not currently sending data
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if (!out_valid) begin
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// Handle keyboard input with priority
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if (kbd_valid) begin
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out_data <= kbd_data;
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out_valid <= 1'b1;
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out_from_uart <= 1'b0;
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kbd_ready <= 1'b0;
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end
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// Handle UART input if no keyboard data
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else if (uart_valid) begin
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out_data <= uart_data;
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out_valid <= 1'b1;
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out_from_uart <= 1'b1;
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uart_ready <= 1'b0;
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end
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// If neither input is valid, stay ready
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else begin
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kbd_ready <= 1'b1;
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uart_ready <= 1'b1;
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end
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end
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end
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end
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endmodule |