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58 lines
2.0 KiB
Verilog
58 lines
2.0 KiB
Verilog
/* ================================================================
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* VT52
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*
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* Copyright (C) 2024 Fred Van Eijk
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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* ================================================================
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*/
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module cursor_blinker
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(input clk,
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input reset,
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input tick,
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input reset_count,
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output wire blink_on
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);
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localparam BITS = 6;
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reg has_incremented;
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reg [BITS-1:0] counter;
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always @(posedge clk) begin
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if (reset) begin
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counter <= 0;
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has_incremented <= 0;
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end
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else if (reset_count) begin
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counter <= 0;
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has_incremented <= tick;
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end
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else if (tick && !has_incremented) begin
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counter <= counter + 1;
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has_incremented <= 1;
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end
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else if (!tick && has_incremented) begin
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has_incremented <= 0;
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end
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end
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assign blink_on = ~counter[BITS-1];
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endmodule
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