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https://github.com/MiSTer-devel/VT52_MiSTer.git
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66 lines
2.3 KiB
Verilog
66 lines
2.3 KiB
Verilog
/* ================================================================
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* VT52
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*
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* Copyright (C) 2024 Fred Van Eijk
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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* ================================================================
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*/
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module cursor
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#(parameter ROW_BITS = 5,
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parameter COL_BITS = 7)
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(input clk,
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input reset,
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input tick,
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output wire [COL_BITS-1:0] x,
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output wire [ROW_BITS-1:0] y,
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output wire blink_on,
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input [COL_BITS-1:0] new_x,
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input [ROW_BITS-1:0] new_y,
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input wen
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);
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cursor_blinker cursor_blinker(.clk(clk),
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.reset(reset),
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.tick(tick),
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.reset_count(wen),
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.blink_on(blink_on)
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);
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simple_register #(.SIZE(COL_BITS))
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cursor_x_reg(.clk(clk),
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.reset(reset),
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.idata(new_x),
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.wen(wen),
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.odata(x)
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);
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simple_register #(.SIZE(ROW_BITS))
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cursor_y_reg(.clk(clk),
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.reset(reset),
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.idata(new_y),
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.wen(wen),
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.odata(y)
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);
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endmodule
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