mirror of
https://github.com/MiSTer-devel/VT52_MiSTer.git
synced 2026-04-19 03:05:47 +00:00
338 lines
8.9 KiB
Systemverilog
338 lines
8.9 KiB
Systemverilog
/* ================================================================
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* VT52
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*
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* Copyright (C) 2024 Fred Van Eijk
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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* ================================================================
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*/
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module emu
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(
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//Master input clock
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input CLK_50M,
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//Async reset from top-level module.
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//Can be used as initial reset.
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input RESET,
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//Must be passed to hps_io module
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inout [48:0] HPS_BUS,
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//Base video clock. Usually equals to CLK_SYS.
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output CLK_VIDEO,
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//Multiple resolutions are supported using different CE_PIXEL rates.
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//Must be based on CLK_VIDEO
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output CE_PIXEL,
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//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
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//if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio.
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output [12:0] VIDEO_ARX,
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output [12:0] VIDEO_ARY,
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output [7:0] VGA_R,
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output [7:0] VGA_G,
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output [7:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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output VGA_DE, // = ~(VBlank | HBlank)
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output VGA_F1,
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output [1:0] VGA_SL,
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output VGA_SCALER, // Force VGA scaler
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output VGA_DISABLE, // analog out is off
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input [11:0] HDMI_WIDTH,
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input [11:0] HDMI_HEIGHT,
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output HDMI_FREEZE,
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output HDMI_BLACKOUT,
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output HDMI_BOB_DEINT,
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`ifdef MISTER_FB
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// Use framebuffer in DDRAM
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output FB_EN,
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output [4:0] FB_FORMAT,
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output [11:0] FB_WIDTH,
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output [11:0] FB_HEIGHT,
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output [31:0] FB_BASE,
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output [13:0] FB_STRIDE,
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input FB_VBL,
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input FB_LL,
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output FB_FORCE_BLANK,
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`ifdef MISTER_FB_PALETTE
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// Palette control for 8bit modes.
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output FB_PAL_CLK,
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output [7:0] FB_PAL_ADDR,
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output [23:0] FB_PAL_DOUT,
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input [23:0] FB_PAL_DIN,
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output FB_PAL_WR,
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`endif
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`endif
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output LED_USER, // 1 - ON, 0 - OFF.
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// b[1]: 0 - LED status is system status OR'd with b[0]
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// 1 - LED status is controled solely by b[0]
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// hint: supply 2'b00 to let the system control the LED.
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output [1:0] LED_POWER,
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output [1:0] LED_DISK,
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// I/O board button press simulation (active high)
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// b[1]: user button
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// b[0]: osd button
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output [1:0] BUTTONS,
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input CLK_AUDIO, // 24.576 MHz
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output [15:0] AUDIO_L,
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output [15:0] AUDIO_R,
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output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
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output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
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//ADC
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inout [3:0] ADC_BUS,
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//SD-SPI
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output SD_SCK,
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output SD_MOSI,
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input SD_MISO,
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output SD_CS,
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input SD_CD,
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//High latency DDR3 RAM interface
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//Use for non-critical time purposes
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output DDRAM_CLK,
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input DDRAM_BUSY,
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output [7:0] DDRAM_BURSTCNT,
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output [28:0] DDRAM_ADDR,
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input [63:0] DDRAM_DOUT,
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input DDRAM_DOUT_READY,
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output DDRAM_RD,
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output [63:0] DDRAM_DIN,
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output [7:0] DDRAM_BE,
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output DDRAM_WE,
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//SDRAM interface with lower latency
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output SDRAM_CLK,
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output SDRAM_CKE,
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output [12:0] SDRAM_A,
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output [1:0] SDRAM_BA,
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inout [15:0] SDRAM_DQ,
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output SDRAM_DQML,
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output SDRAM_DQMH,
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output SDRAM_nCS,
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output SDRAM_nCAS,
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output SDRAM_nRAS,
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output SDRAM_nWE,
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`ifdef MISTER_DUAL_SDRAM
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//Secondary SDRAM
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input SDRAM2_EN,
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output SDRAM2_CLK,
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output [12:0] SDRAM2_A,
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output [1:0] SDRAM2_BA,
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inout [15:0] SDRAM2_DQ,
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output SDRAM2_nCS,
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output SDRAM2_nCAS,
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output SDRAM2_nRAS,
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output SDRAM2_nWE,
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`endif
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input UART_CTS,
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output UART_RTS,
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input UART_RXD,
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output UART_TXD,
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output UART_DTR,
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input UART_DSR,
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// Open-drain User port.
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// 0 - D+/RX
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// 1 - D-/TX
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// 2..6 - USR2..USR6
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// Set USER_OUT to 1 to read from USER_IN.
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input [6:0] USER_IN,
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output [6:0] USER_OUT,
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input OSD_STATUS
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);
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///////// Default values for ports not used in this core /////////
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assign ADC_BUS = 'Z;
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assign {UART_RTS, UART_DTR} = 0;
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assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
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assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
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assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = '0;
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assign VGA_SL = 0;
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assign VGA_F1 = 0;
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assign VGA_SCALER = 1;
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assign VGA_DISABLE = 0;
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assign HDMI_FREEZE = 0;
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assign HDMI_BOB_DEINT = 0;
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assign AUDIO_S = 0;
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assign AUDIO_L = 0;
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assign AUDIO_R = 0;
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assign AUDIO_MIX = 0;
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assign LED_DISK = 0;
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assign LED_POWER = 0;
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assign BUTTONS = 0;
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//////////////////////////////////////////////////////////////////
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wire [1:0] ar = status[122:121];
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assign VIDEO_ARX = (!ar) ? 12'd4 : (ar - 1'd1);
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assign VIDEO_ARY = (!ar) ? 12'd3 : 12'd0;
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// enable input on USER_IO[0] for UART i.e. USER_IN[0] rx
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assign USER_OUT[0] = 1'b1;
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`include "build_id.v"
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localparam CONF_STR = {
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"VT52;;",
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"-;",
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"O[122:121],Aspect ratio,Original (4:3),Full Screen;",
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"O[4:3],Text Color,White,Red,Green,Blue;",
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"OC,Serial Port,User IO Port,Console Port;",
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"OE,Font,Terminus 8x16, VT52 rom 8x8;",
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"-;",
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"T[0],Reset;",
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"R[0],Reset and close OSD;",
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"V,v",`BUILD_DATE
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};
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/////////////////////// CLOCKS ///////////////////////////////
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wire locked;
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pll pll
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(
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.refclk(CLK_50M),
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.rst(0),
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.outclk_0(CLK_VIDEO),
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.locked(locked)
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);
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wire forced_scandoubler;
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wire [1:0] buttons;
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wire [127:0] status;
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wire ps2_clk, ps2_data;
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hps_io #(.CONF_STR(CONF_STR), .PS2DIV(800)) hps_io
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(
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.clk_sys(CLK_VIDEO),
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.HPS_BUS(HPS_BUS),
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.EXT_BUS(),
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.gamma_bus(),
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.forced_scandoubler(forced_scandoubler),
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.buttons(buttons),
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.status(status),
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.status_menumask({status[5]}),
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.ps2_kbd_clk_out(ps2_clk),
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.ps2_kbd_data_out(ps2_data)
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);
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wire reset = RESET | status[0] | buttons[1];
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// Generate CE_PIXEL for ~14.7MHz from 29.4MHz
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reg ce_pix;
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always @(posedge CLK_VIDEO) begin
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reg div; // Single bit for divide by 2
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div <= div + 1'd1;
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ce_pix <= !div;
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end
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wire HBlank;
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wire HSync;
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wire VBlank;
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wire VSync;
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wire video_out;
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assign CE_PIXEL = ce_pix;
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assign VGA_DE = ~(HBlank | VBlank);
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assign VGA_HS = HSync;
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assign VGA_VS = VSync;
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// Color selection
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reg [7:0] R, G, B;
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always @(posedge CLK_VIDEO) begin
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case (status[4:3])
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2'b00: begin // White
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R <= {8{video_out}};
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G <= {8{video_out}};
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B <= {8{video_out}};
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end
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2'b01: begin // Red
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R <= {8{video_out}};
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G <= 8'd0;
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B <= 8'd0;
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end
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2'b10: begin // Green
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R <= 8'd0;
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G <= {8{video_out}};
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B <= 8'd0;
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end
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2'b11: begin // Blue
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R <= 8'd0;
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G <= 8'd0;
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B <= {8{video_out}};
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end
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endcase
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end
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assign VGA_R = R;
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assign VGA_G = G;
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assign VGA_B = B;
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// UART port selection logic
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wire uart_tx_wire;
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wire uart_rx_wire = !status[12] ? USER_IN[0] : UART_RXD;
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assign UART_TXD = !status[12] ? 1'b1 : uart_tx_wire;
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assign USER_OUT[1] = !status[12] ?
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uart_tx_wire : // When USER_IO selected
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1'b1; // When UART selected
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VT52_terminal vt52_inst
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(
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.clk(CLK_VIDEO),
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.reset(reset),
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.ce_pix(ce_pix),
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.font_8x8(status[14]),
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.hsync(HSync),
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.vsync(VSync),
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.hblank(HBlank),
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.vblank(VBlank),
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.video(video_out),
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.led(LED_USER),
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.ps2_data(ps2_data),
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.ps2_clk(ps2_clk),
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.uart_tx(uart_tx_wire),
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.uart_rx(uart_rx_wire)
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);
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endmodule |