mister-devel/Template_MiSTer
1
0
Fork 0
mirror of https://github.com/MiSTer-devel/Template_MiSTer.git synced 2026-05-24 03:04:36 +00:00
Code Issues Packages Projects Releases Wiki Activity

FB mode signal to HPS.

Browse Source
This commit is contained in:
Sorgelig
2022-01-31 23:14:05 +08:00
parent 51b3685c5f
commit 24116a17cd
3 changed files with 8 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
mycore.sv
View File

@@ -26,7 +26,7 @@ module emu
input RESET,
//Must be passed to hps_io module
inout [47:0] HPS_BUS,
inout [48:0] HPS_BUS,
//Base video clock. Usually equals to CLK_SYS.
output CLK_VIDEO,

4
sys/hps_io.sv
View File

@@ -30,7 +30,7 @@
module hps_io #(parameter CONF_STR, CONF_STR_BRAM=1, PS2DIV=0, WIDE=0, VDNUM=1, BLKSZ=2, PS2WE=0)
(
input clk_sys,
inout [47:0] HPS_BUS,
inout [48:0] HPS_BUS,
// buttons up to 32
output reg [31:0] joystick_0,
@@ -316,7 +316,7 @@ always@(posedge clk_sys) begin : uio_block
'h0X17,
'h0X18: begin sd_ack <= disk[VD:0]; sdn_ack <= io_din[11:8]; end
'h29: io_dout <= {4'hA, stflg};
'h2B: io_dout <= {HPS_BUS[47:46],4'b0010};
'h2B: io_dout <= {HPS_BUS[48:46],4'b0010};
'h2F: io_dout <= 1;
'h32: io_dout <= gamma_bus[21];
'h36: begin io_dout <= info_n; info_n <= 0; end

6
sys/sys_top.v
View File

@@ -1522,11 +1522,15 @@ wire [13:0] fb_stride;
assign fb_stride = 0;
`endif
reg [1:0] sl_r;
wire [1:0] sl = sl_r;
always @(posedge clk_sys) sl_r <= FB_EN ? 2'b00 : scanlines;
emu emu
(
.CLK_50M(FPGA_CLK2_50),
.RESET(reset),
.HPS_BUS({scanlines,f1, HDMI_TX_VS,
.HPS_BUS({fb_en, sl, f1, HDMI_TX_VS,
clk_100m, clk_ihdmi,
ce_hpix, hde_emu, hhs_fix, hvs_fix,
io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}),