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https://github.com/MiSTer-devel/TK2000_MiSTer.git
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211 lines
7.4 KiB
Verilog
211 lines
7.4 KiB
Verilog
/*
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Multicore 2 / Multicore 2+
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Copyright (c) 2017-2020 - Victor Trucco
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All rights reserved
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Redistribution and use in source and synthezised forms, with or without
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modification, are permitted provided that the following conditions are met:
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Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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Redistributions in synthesized form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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Neither the name of the author nor the names of other contributors may
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be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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You are responsible for any legal issues arising from your use of this code.
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*///
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// sdram.v
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//
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// apple II version of the sdram controller implementation for the
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// MiST board
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// http://code.google.com/p/mist-board/
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//
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// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module sdram (
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// interface to the MT48LC16M16 chip
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inout reg [15:0] sd_data, // 16 bit bidirectional data bus
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output reg [12:0] sd_addr, // 13 bit multiplexed address bus
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output reg [1:0] sd_dqm, // two byte masks
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output reg [1:0] sd_ba, // two banks
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output sd_cs, // a single chip select
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output sd_we, // write enable
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output sd_ras, // row address select
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output sd_cas, // columns address select
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// cpu/chipset interface
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input init, // init signal after FPGA config to initialize RAM
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input clk, // sdram is accessed at up to 128MHz
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input clkref, // reference clock to sync to
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input [7:0] din, // data input from chipset/cpu
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output [15:0] dout, // data output to chipset/cpu
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input aux,
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input [24:0] addr, // 25 bit byte address
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input we // cpu/chipset requests write
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);
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// no burst configured
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localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 3 cycles@128MHz
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localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8
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localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
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localparam CAS_LATENCY = 3'd3; // 2/3 allowed
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localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
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localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
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localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
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// ---------------------------------------------------------------------
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// ------------------------ cycle state machine ------------------------
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// ---------------------------------------------------------------------
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localparam STATE_IDLE = 3'd0; // first state in cycle
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localparam STATE_CMD_START = 3'd0; // state in which a new command can be started
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localparam STATE_CMD_CONT = STATE_CMD_START + RASCAS_DELAY; // 4 command can be continued
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localparam STATE_READ = STATE_CMD_CONT + CAS_LATENCY + 4'd1; //
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localparam STATE_LAST = 3'd7; // last state in cycle
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assign dout = sd_data;
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reg [3:0] q /* synthesis noprune */;
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always @(posedge clk) begin
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// 112Mhz counter synchronous to 14 Mhz clock
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// force counter to pass state 5->6 exactly after the rising edge of clkref
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// since clkref is two clocks early
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if(((q == 13) && ( clkref == 0)) ||
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((q == 0) && ( clkref == 1)) ||
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((q != 13) && (q != 0))) begin
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if( q != 13)
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q <= q + 4'd1;
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else
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q <= 4'd0;
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end
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end
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// ---------------------------------------------------------------------
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// --------------------------- startup/reset ---------------------------
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// ---------------------------------------------------------------------
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// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
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// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
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reg [4:0] reset;
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always @(posedge clk) begin
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if(init) reset <= 5'h1f;
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else if((q == STATE_LAST) && (reset != 0))
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reset <= reset - 5'd1;
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end
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// ---------------------------------------------------------------------
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// ------------------ generate ram control signals ---------------------
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// ---------------------------------------------------------------------
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// all possible commands
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localparam CMD_INHIBIT = 4'b1111;
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localparam CMD_NOP = 4'b0111;
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localparam CMD_ACTIVE = 4'b0011;
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localparam CMD_READ = 4'b0101;
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localparam CMD_WRITE = 4'b0100;
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localparam CMD_BURST_TERMINATE = 4'b0110;
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localparam CMD_PRECHARGE = 4'b0010;
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localparam CMD_AUTO_REFRESH = 4'b0001;
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localparam CMD_LOAD_MODE = 4'b0000;
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reg [3:0] sd_cmd; // current command sent to sd ram
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// drive control signals according to current command
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assign sd_cs = sd_cmd[3];
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assign sd_ras = sd_cmd[2];
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assign sd_cas = sd_cmd[1];
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assign sd_we = sd_cmd[0];
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always @(posedge clk) begin
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sd_cmd <= CMD_INHIBIT; // default: idle
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sd_data <= 16'bZ;
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if(reset != 0) begin
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// initialization takes place at the end of the reset phase
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if(q == STATE_CMD_START) begin
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if(reset == 13) begin
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sd_cmd <= CMD_PRECHARGE;
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sd_addr[10] <= 1'b1; // precharge all banks
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end
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if(reset == 2) begin
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sd_cmd <= CMD_LOAD_MODE;
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sd_addr <= MODE;
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end
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end
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end else begin
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// normal operation
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// ------------------- cpu/chipset read/write ----------------------
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// RAS phase
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if(q == STATE_CMD_START) begin
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sd_cmd <= CMD_ACTIVE;
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sd_addr <= addr[21:9];
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sd_ba <= addr[23:22];
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// always return both bytes in a read. Only the correct byte
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// is being stored during read. On write only one of the two
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// bytes is enabled
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if(!we) sd_dqm <= 2'b00;
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else sd_dqm <= { ~aux, aux };
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end
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// CAS phase
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if(q == STATE_CMD_CONT) begin
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sd_cmd <= we?CMD_WRITE:CMD_READ;
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if (we) sd_data <= {din, din};
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sd_addr <= { 4'b0010, addr[8:0] }; // auto precharge
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end
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// always add a refresh cycle
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if(q == 8)
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sd_cmd <= CMD_AUTO_REFRESH;
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end
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end
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endmodule
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