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https://github.com/MiSTer-devel/SuperVision_MiSTer.git
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433 lines
11 KiB
Systemverilog
433 lines
11 KiB
Systemverilog
//============================================================================
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//
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//============================================================================
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module emu
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(
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//Master input clock
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input CLK_50M,
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//Async reset from top-level module.
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//Can be used as initial reset.
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input RESET,
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//Must be passed to hps_io module
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inout [48:0] HPS_BUS,
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//Base video clock. Usually equals to CLK_SYS.
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output CLK_VIDEO,
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//Multiple resolutions are supported using different CE_PIXEL rates.
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//Must be based on CLK_VIDEO
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output CE_PIXEL,
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//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
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//if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio.
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output [12:0] VIDEO_ARX,
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output [12:0] VIDEO_ARY,
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output [7:0] VGA_R,
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output [7:0] VGA_G,
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output [7:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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output VGA_DE, // = ~(VBlank | HBlank)
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output VGA_F1,
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output [1:0] VGA_SL,
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output VGA_SCALER, // Force VGA scaler
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input [11:0] HDMI_WIDTH,
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input [11:0] HDMI_HEIGHT,
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output HDMI_FREEZE,
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`ifdef MISTER_FB
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// Use framebuffer in DDRAM (USE_FB=1 in qsf)
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// FB_FORMAT:
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// [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
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// [3] : 0=16bits 565 1=16bits 1555
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// [4] : 0=RGB 1=BGR (for 16/24/32 modes)
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//
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// FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes)
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output FB_EN,
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output [4:0] FB_FORMAT,
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output [11:0] FB_WIDTH,
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output [11:0] FB_HEIGHT,
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output [31:0] FB_BASE,
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output [13:0] FB_STRIDE,
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input FB_VBL,
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input FB_LL,
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output FB_FORCE_BLANK,
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`ifdef MISTER_FB_PALETTE
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// Palette control for 8bit modes.
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// Ignored for other video modes.
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output FB_PAL_CLK,
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output [7:0] FB_PAL_ADDR,
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output [23:0] FB_PAL_DOUT,
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input [23:0] FB_PAL_DIN,
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output FB_PAL_WR,
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`endif
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`endif
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output LED_USER, // 1 - ON, 0 - OFF.
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// b[1]: 0 - LED status is system status OR'd with b[0]
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// 1 - LED status is controled solely by b[0]
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// hint: supply 2'b00 to let the system control the LED.
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output [1:0] LED_POWER,
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output [1:0] LED_DISK,
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// I/O board button press simulation (active high)
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// b[1]: user button
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// b[0]: osd button
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output [1:0] BUTTONS,
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input CLK_AUDIO, // 24.576 MHz
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output [15:0] AUDIO_L,
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output [15:0] AUDIO_R,
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output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
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output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
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//ADC
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inout [3:0] ADC_BUS,
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//SD-SPI
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output SD_SCK,
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output SD_MOSI,
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input SD_MISO,
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output SD_CS,
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input SD_CD,
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//High latency DDR3 RAM interface
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//Use for non-critical time purposes
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output DDRAM_CLK,
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input DDRAM_BUSY,
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output [7:0] DDRAM_BURSTCNT,
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output [28:0] DDRAM_ADDR,
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input [63:0] DDRAM_DOUT,
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input DDRAM_DOUT_READY,
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output DDRAM_RD,
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output [63:0] DDRAM_DIN,
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output [7:0] DDRAM_BE,
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output DDRAM_WE,
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//SDRAM interface with lower latency
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output SDRAM_CLK,
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output SDRAM_CKE,
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output [12:0] SDRAM_A,
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output [1:0] SDRAM_BA,
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inout [15:0] SDRAM_DQ,
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output SDRAM_DQML,
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output SDRAM_DQMH,
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output SDRAM_nCS,
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output SDRAM_nCAS,
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output SDRAM_nRAS,
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output SDRAM_nWE,
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`ifdef MISTER_DUAL_SDRAM
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//Secondary SDRAM
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//Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0
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input SDRAM2_EN,
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output SDRAM2_CLK,
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output [12:0] SDRAM2_A,
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output [1:0] SDRAM2_BA,
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inout [15:0] SDRAM2_DQ,
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output SDRAM2_nCS,
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output SDRAM2_nCAS,
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output SDRAM2_nRAS,
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output SDRAM2_nWE,
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`endif
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input UART_CTS,
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output UART_RTS,
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input UART_RXD,
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output UART_TXD,
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output UART_DTR,
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input UART_DSR,
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// Open-drain User port.
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// 0 - D+/RX
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// 1 - D-/TX
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// 2..6 - USR2..USR6
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// Set USER_OUT to 1 to read from USER_IN.
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input [6:0] USER_IN,
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output [6:0] USER_OUT,
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input OSD_STATUS
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);
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///////// Default values for ports not used in this core /////////
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assign ADC_BUS = 'Z;
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assign USER_OUT[6:4] = '1;
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assign {UART_RTS, UART_TXD, UART_DTR} = 0;
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assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
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assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
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assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = '0;
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assign VGA_SL = scale ? scale - 1'd1 : 2'd0;
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assign VGA_F1 = 0;
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assign VGA_SCALER = 0;
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assign AUDIO_S = 0;
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assign AUDIO_MIX = status[23:22];
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assign LED_DISK = 0;
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assign LED_POWER = 0;
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assign LED_USER = 0;
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assign BUTTONS = 0;
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assign HDMI_FREEZE = 0;
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wire [7:0] link_data, link_ddr;
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assign USER_OUT[3:0] = (link_ddr[3:0] | link_data[3:0]);
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//////////////////////////////////////////////////////////////////
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wire [1:0] scale = status[3:2];
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wire [1:0] ar = status[122:121];
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`include "build_id.v"
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localparam CONF_STR = {
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"SuperVision;;",
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"-;",
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"F1,binsv,Load Cartridge;",
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"-;",
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"O[122:121],Aspect ratio,Original,Full Screen,[ARC1],[ARC2];",
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"O[20],Flickerblend,On,Off;",
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"O[21],Framerate,60hz,Original;",
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"O[3:2],Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
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"O[11:10],Scale,Normal,V-Integer,Narrower HV-Integer,Wider HV-Integer;",
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"O[23:22],Center Audio,Off,25%,50%,100%;",
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"-;",
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"O7,Custom Palette,Off,On;",
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"D0FC3,SGBGBP,Load Palette;",
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"-;",
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"R0,Reset;",
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"J0,B,A,select,start;",
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"V,v",`BUILD_DATE
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};
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wire forced_scandoubler;
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wire [15:0] joystick_0;
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wire [1:0] buttons;
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wire [127:0] status;
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wire [10:0] ps2_key;
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wire [24:0] ioctl_addr;
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wire [7:0] ioctl_dout;
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wire [7:0] ioctl_index;
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wire ioctl_wr;
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wire ioctl_download;
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wire ioctl_wait;
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wire [21:0] gamma_bus;
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wire rom_download = (~|ioctl_index[5:0] || ioctl_index[5:0] == 1) && ioctl_download;
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hps_io #(.CONF_STR(CONF_STR)) hps_io
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(
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.clk_sys(clk_sys),
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.HPS_BUS(HPS_BUS),
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.gamma_bus(gamma_bus),
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.forced_scandoubler(forced_scandoubler),
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.buttons(buttons),
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.status(status),
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.status_menumask({~status[7]}),
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.ps2_key(ps2_key),
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.joystick_0(joystick_0),
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.ioctl_download(ioctl_download),
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.ioctl_wr(ioctl_wr),
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.ioctl_addr(ioctl_addr),
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.ioctl_dout(ioctl_dout),
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.ioctl_wait(ioctl_wait),
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.ioctl_index(ioctl_index)
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);
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wire clk_sys;
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wire clk_vid; // Make a different clock to seperate intent in case the video rate needs change
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wire clk_ram;
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wire clock_locked;
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pll pll
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(
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.refclk(CLK_50M),
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.rst(0),
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.outclk_0(clk_ram), // 50
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.outclk_1(clk_sys), // 9
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.locked(clock_locked)
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);
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assign clk_vid = clk_sys;
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wire ce_pix;
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wire freeze_sync;
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wire hsync;
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wire vsync;
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wire hblank;
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wire vblank;
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wire vga_de;
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wire [8:0] red, green, blue;
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wire palette_download = (ioctl_index[5:0] == 3) && ioctl_download;
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wire reset = RESET | status[0] | buttons[1] | rom_download;
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assign CLK_VIDEO = clk_vid;
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wire [7:0] rom_dout;
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wire [18:0] rom_addr;
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wire [1:0] last_pixel, pixel, prev_pixel;
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wire rom_cs;
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reg [14:0] vbuffer_addr;
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wire cart_busy;
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reg [18:0] rom_mask = 19'h7FFFF;
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assign ioctl_wait = cart_busy & rom_download;
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supervision supervision
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(
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.clk_sys (clk_sys),
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.reset (reset),
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.joystick (joystick_0),
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.rom_dout (rom_dout),
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.user_in (USER_IN[3:0]),
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.compat60 (~status[21]),
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.large_rom (|rom_mask[18:17]),
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.hsync (hsync),
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.vsync (vsync),
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.hblank (hblank),
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.vblank (vblank),
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.audio_r (AUDIO_R),
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.audio_l (AUDIO_L),
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.pixel (pixel),
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.pix_ce (ce_pix),
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.addr_bus (rom_addr),
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.rom_read (rom_cs),
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.link_data (link_data),
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.link_ddr (link_ddr)
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);
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logic [127:0] user_palette = 128'h87BA6B_6BA378_386B82_384052_0000_0000;
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wire [127:0] default_palette = 128'h87BA6B_6BA378_386B82_384052_0000_0000;
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logic [2:0][7:0] palette[4];
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assign palette[0] = status[7] ? user_palette[127:104] : default_palette[127:104];
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assign palette[1] = status[7] ? user_palette[103:80] : default_palette[103:80];
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assign palette[2] = status[7] ? user_palette[79:56] : default_palette[79:56];
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assign palette[3] = status[7] ? user_palette[55:32] : default_palette[55:32];
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always @(posedge clk_vid) begin
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if (ce_pix) begin
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red <= ~status[20] ? (({1'b0, palette[pixel][2]} + palette[prev_pixel][2]) >> 1'd1) : palette[pixel][2];
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green <= ~status[20] ? (({1'b0, palette[pixel][1]} + palette[prev_pixel][1]) >> 1'd1) : palette[pixel][1];
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blue <= ~status[20] ? (({1'b0, palette[pixel][0]} + palette[prev_pixel][0]) >> 1'd1) : palette[pixel][0];
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last_pixel <= pixel;
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if (~vblank && ~hblank)
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vbuffer_addr <= vbuffer_addr + 1'd1;
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if (vsync)
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vbuffer_addr <= 0;
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end
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end
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dpram #(.data_width(2), .addr_width(15)) vbuffer (
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.clock (clk_sys),
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.address_a (vbuffer_addr - 1'd1),
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.data_a (last_pixel),
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.wren_a (~vblank && ~hblank && CE_PIXEL),
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.address_b (vbuffer_addr),
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.q_b (prev_pixel)
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);
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always @(posedge clk_sys) begin
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if (rom_download && ioctl_wr)
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rom_mask <= ioctl_addr[18:0];
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if (palette_download)
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user_palette[{~ioctl_addr[3:0], 3'b000}+:8] <= ioctl_dout;
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end
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sdram cart_rom
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(
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.SDRAM_DQ (SDRAM_DQ),
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.SDRAM_A (SDRAM_A),
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.SDRAM_DQML (SDRAM_DQML),
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.SDRAM_DQMH (SDRAM_DQMH),
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.SDRAM_BA (SDRAM_BA),
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.SDRAM_nCS (SDRAM_nCS),
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.SDRAM_nWE (SDRAM_nWE),
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.SDRAM_nRAS (SDRAM_nRAS),
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.SDRAM_nCAS (SDRAM_nCAS),
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.SDRAM_CLK (SDRAM_CLK),
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.SDRAM_CKE (SDRAM_CKE),
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.init (!clock_locked),
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.clk (clk_ram),
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.ch0_addr (rom_download ? ioctl_addr : (rom_addr & rom_mask)),
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.ch0_rd (rom_cs && ~rom_download),
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.ch0_wr (rom_download & ioctl_wr),
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.ch0_din (ioctl_dout),
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.ch0_dout (rom_dout),
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.ch0_busy (cart_busy)
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);
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video_freak video_freak
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(
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.*,
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.VGA_DE_IN (vga_de),
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.VGA_DE (VGA_DE),
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.ARX ((!ar) ? 12'd1 : (ar - 1'd1)),
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.ARY ((!ar) ? 12'd1 : 12'd0),
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.CROP_SIZE (0),
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.CROP_OFF (0),
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.SCALE (status[11:10])
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);
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video_mixer #(640, 0) mixer
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(
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.*,
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.CE_PIXEL (CE_PIXEL),
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.hq2x (scale == 1),
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.scandoubler (scale || forced_scandoubler),
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.gamma_bus (gamma_bus),
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.R (red[7:0]),
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.G (green[7:0]),
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.B (blue[7:0]),
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.HSync (hsync),
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.VSync (vsync),
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.HBlank (hblank),
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.VBlank (vblank),
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.VGA_R (VGA_R),
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.VGA_G (VGA_G),
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.VGA_B (VGA_B),
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.VGA_VS (VGA_VS),
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.VGA_HS (VGA_HS),
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.VGA_DE (vga_de)
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);
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endmodule
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