David Hunter 258442b68c epochtv1: CPU ownership of VRAM bus is tied to RDB/WRB ...

- Fix WAITB timing to be 1 cycle on writes
- Fix effect of RDB posedge on WAITB
- Cycle timing now verified to match HW for block instruction VRAM copies

2025-08-30 21:32:29 -07:00

..

epochtv1.txt

epochtv1: CPU ownership of VRAM bus is tied to RDB/WRB

2025-08-30 21:32:29 -07:00

notes.txt

upd7800: Implement \WAIT input

2024-12-27 22:27:47 -08:00

scan-rom.py

scv: Implement cartridge ID and automatic mapper selection

2024-09-02 23:42:59 -07:00

upd1771c.txt

Document uPD1771C pinout

2024-12-29 18:57:59 -08:00