mister-devel/SuperCassetteVision_MiSTer
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Commit Graph

  • 0deb3ec4bc Update sys dev David Hunter 2025-09-07 11:06:15 -07:00
  • 16e5bf752c Release 20250906 (really) main David Hunter 2025-09-06 22:48:20 -07:00
  • bb38c29e32 Release 20250906 David Hunter 2025-09-06 22:20:25 -07:00
  • 0b82a8e4e2 Merge remote-tracking branch 'origin/main' into dev David Hunter 2025-09-06 21:57:20 -07:00
  • 5d9d315749 epochtv1: Make overscan mask user-configurable David Hunter 2025-09-06 18:27:15 -07:00
  • 2a1a8bced1 epochtv1: Fix spr_nc might stay high after sofp_row_end David Hunter 2025-09-03 22:27:02 -07:00
  • 847dbfff6e epochtv1: More accurate VRAM address bus computation David Hunter 2025-09-02 23:34:32 -07:00
  • 4187c26330 [temp] Speed up CPU clock to match my HW: 2.03MHz faster-cpu David Hunter 2025-08-30 21:41:02 -07:00
  • 258442b68c epochtv1: CPU ownership of VRAM bus is tied to RDB/WRB David Hunter 2025-08-30 21:32:29 -07:00
  • f9a18fdf83 upd7800: BLOCK cycles should be idle (M2), read (M3), write (M4) David Hunter 2025-08-29 23:12:27 -07:00
  • 012beff0a1 upd7800: RDB should assert in T1 on CP1 rising David Hunter 2025-08-29 22:53:18 -07:00
  • 13db5a90e4 epochtv1: Re-observe WAITB and implement address-based state machine David Hunter 2025-08-28 21:49:38 -07:00
  • bc8dd33f5f epochtv1: Remove SOFP 2-color flush state David Hunter 2025-08-25 21:34:44 -07:00
  • 36c4d5ae85 epochtv1: Hide overscan David Hunter 2025-08-25 19:56:08 -07:00
  • 91715ed880 epochtv1: Fix OAM copy timing and CPU access during David Hunter 2025-08-24 22:00:54 -07:00
  • e25306dfe7 epochtv1: Fix interaction of sprite split attribute and 2-color mode David Hunter 2025-08-24 01:02:13 -07:00
  • a0c2db1dbe epochtv1: Fix 2-color sprite color transform David Hunter 2025-08-23 18:03:32 -07:00
  • 62165f0348 Add render_tb VRAM binaries David Hunter 2025-08-23 17:57:55 -07:00
  • 944856179b epochtv1: Fix sprite width and 2-color handling David Hunter 2025-08-21 20:54:27 -07:00
  • 0e007c4689 Update scv_tb .gtkw David Hunter 2025-08-17 20:52:36 -07:00
  • be48df1102 epochtv1: Implement R0.3 = disable OAM copy David Hunter 2025-08-17 19:05:25 -07:00
  • e4bb5e5960 epochtv1: Add control register shadow copy David Hunter 2025-08-17 18:28:43 -07:00
  • 9bb4bdee77 epochtv1: Fix shadow terminology David Hunter 2025-08-17 18:18:44 -07:00
  • 8be787aec3 epochtv1: Registers are write-only David Hunter 2025-08-17 17:49:47 -07:00
  • ffcaa576d6 epochtv1: Tidy row parameters David Hunter 2025-08-17 17:25:22 -07:00
  • 1f848e9070 epochtv1: More accurate BGM / OAM / VRAM access David Hunter 2025-08-17 17:05:52 -07:00
  • 6ea5f74a54 Update readme with current status David Hunter 2025-05-26 22:06:28 -07:00
  • ce0632dde1 epochtv1: Use start_line as current row counter David Hunter 2025-04-20 19:55:26 -07:00
  • 75e5fcf546 epochtv1: Cap sprite eval+render at 251 VRAM bus cycles David Hunter 2025-04-14 21:02:24 -07:00
  • 7f147e954d epochtv1: render sprites two rows at a time David Hunter 2025-04-11 21:27:14 -07:00
  • 3c2282bd95 epochtv1: Tweak docs David Hunter 2025-04-06 13:19:52 -07:00
  • 0e2651042e epochtv1: Document background rendering details David Hunter 2025-03-23 22:10:33 -07:00
  • aeac73c482 epochtv1: More sprite rendering David Hunter 2025-03-02 23:00:27 -08:00
  • a17d728916 Fix row numbers David Hunter 2025-02-17 22:23:23 -08:00
  • cfa1d96faa epochtv1: Sprite rendering David Hunter 2025-02-17 20:07:28 -08:00
  • 9c5d0981a5 Lower D1771C clock to 5.0MHz upd1771c-firefox David Hunter 2025-02-01 17:22:53 -08:00
  • 97e5c41d85 Firefox seems to be tooting now David Hunter 2025-02-01 16:37:45 -08:00
  • 11a898a818 upd1771c: Implement ALU ops MD, n David Hunter 2025-02-01 15:59:18 -08:00
  • 4138632089 Clear APU PA latch on reset David Hunter 2025-02-01 15:58:46 -08:00
  • 21617fd131 upd1771c: Reorder ID code to match vertical position in decoder David Hunter 2025-02-01 15:57:59 -08:00
  • 380837a913 Change uPD1771C to ROM -011, latch its PA inputs, and test David Hunter 2025-01-31 23:00:45 -08:00
  • 32cb8510e5 Testing the uPD1771C-011 ROM from Grandstand Firefox F-7 David Hunter 2025-01-31 22:01:13 -08:00
  • d1cdb2ec74 Release 20250131 David Hunter 2025-01-31 21:07:42 -08:00
  • 26a15b6c3f epochtv1: Add OSD option to select RGB vs. RF color palette David Hunter 2025-01-26 22:49:16 -08:00
  • 198c4a84c4 epochtv1: Mimic RGB connector signal level fall off David Hunter 2025-01-22 22:18:03 -08:00
  • b3953734e6 epochtv1: Align background and sprites to render window David Hunter 2025-01-20 20:58:45 -08:00
  • 77c5c5e36b epochtv1: Output the full render area, minus the edges David Hunter 2025-01-20 14:54:35 -08:00
  • 0fc325cb88 epochtv1: Document screen size, char/sprite render coordinates David Hunter 2025-01-20 14:13:59 -08:00
  • 157af22018 upd7800: DAA does not clear the HC flag David Hunter 2025-01-18 22:28:05 -08:00
  • 6904332527 upd7800: BLOCK ignores SK flag David Hunter 2025-01-18 22:25:34 -08:00
  • 0874281f08 upd7800: $xx + $xF + 1 (carry in) sets HC=1 David Hunter 2025-01-18 22:22:30 -08:00
  • 6b4017ef1a Release 20241231 David Hunter 2024-12-31 23:59:35 -08:00
  • 561464e588 upd7800: Fix STM following skipped instruction David Hunter 2024-12-31 23:26:40 -08:00
  • 1c0f8e6162 upd7800: BLOCK: Don't use skip to stop repeat David Hunter 2024-12-31 19:34:08 -08:00
  • ffd25540e3 upd7800: Correct cycle count of special reg. instructions David Hunter 2024-12-31 18:19:51 -08:00
  • f576f3ed7c upd7800: Latch cl_skip to avoid invalidation by interrupt David Hunter 2024-12-31 17:23:20 -08:00
  • a85d0627c6 upd7800: M1 should stay low during interrupt entry David Hunter 2024-12-31 17:21:53 -08:00
  • 2e9cd25399 upd7800: Trim unneeded idle cycles from move ins. ucode David Hunter 2024-12-31 16:15:48 -08:00
  • 1a374e4f36 upd7800: Remove vestigial skipn field from ird table David Hunter 2024-12-31 15:04:51 -08:00
  • 8e741f8bd5 scv: Change CPU clock to 2.000000 MHz David Hunter 2024-12-30 09:57:51 -08:00
  • 2992b04f3c upd7800: Edge-triggered interrupts sampled at CP1 David Hunter 2024-12-30 09:37:01 -08:00
  • 258467168e upd7800: Skipping instructions should not optimize cycles David Hunter 2024-12-29 23:02:38 -08:00
  • 01a25d0385 Document uPD1771C pinout David Hunter 2024-12-29 18:57:59 -08:00
  • e7900d1019 Implement Epoch TV-1 SCPUB and WAITB David Hunter 2024-12-28 17:37:56 -08:00
  • c7086e691c upd7800: Implement \WAIT input David Hunter 2024-12-27 21:56:19 -08:00
  • 53962b75bc Document Epoch TV-1 pinout David Hunter 2024-12-25 19:33:21 -08:00
  • 3df73a1bde upd1771c: Comments on NS interrupt / PNC trigger David Hunter 2024-12-21 17:27:58 -08:00
  • e326e773e1 Merge branch 'd1771c' David Hunter 2024-12-18 21:22:20 -08:00
  • d87a7e2f1e epochtv1: Match video timing to actual HW David Hunter 2024-12-16 22:18:08 -08:00
  • 8695100218 upd1771c: Fix name of JMP-related node David Hunter 2024-12-16 22:09:08 -08:00
  • 72c786a758 upd1771c: Implement NSS / PNC2 David Hunter 2024-12-09 00:05:51 -08:00
  • 6b7a960e96 upd1771c: Updates names to match schematic David Hunter 2024-12-08 21:27:26 -08:00
  • f2fab65cf4 Found a uPD1771 designer's website David Hunter 2024-12-08 18:16:43 -08:00
  • 51b23d38d5 upd1771c: Implement timer counter and RG LFSR David Hunter 2024-11-27 12:33:15 -08:00
  • 2c0cac6fb1 Release 20241124 David Hunter 2024-11-24 19:49:10 -08:00
  • f3c2ee989d Update boot.rom docs for uPD1771C David Hunter 2024-11-24 19:17:06 -08:00
  • 5f08a4dd8b scv: Load uPD1771C ROM dynamically David Hunter 2024-11-24 18:17:23 -08:00
  • c5ef2b4128 Correct Star Speeder ROM assembly instructions David Hunter 2024-11-23 09:09:31 -08:00
  • 6445b04e49 upd7800: Mask PC control function outputs David Hunter 2024-11-23 09:07:27 -08:00
  • 1e3692f927 upd1771c: Fix "TANDINZ (H), n" decode David Hunter 2024-11-22 19:42:08 -08:00
  • 2e30d4d062 upd1771c: Add a testbench to play a digital packet David Hunter 2024-11-22 09:29:36 -08:00
  • c2937e0c14 scv: Fix audio clock generator logic David Hunter 2024-11-20 21:41:23 -08:00
  • 0c8af3d177 scv: Speed up audio clock until it sounds right David Hunter 2024-11-19 21:30:17 -08:00
  • 7897b0c7d3 upd1771c: Synchronize tone_tb with chip sim. testsong.js timing David Hunter 2024-11-17 20:04:53 -08:00
  • 30b43e519f upd1771c: Align NC reset behavior with chip sim. David Hunter 2024-11-17 19:54:29 -08:00
  • 9d1b2ea67e Fix hole in N range handling David Hunter 2024-11-16 21:58:59 -08:00
  • 9fe3100d5c Implement shadow skip David Hunter 2024-11-16 20:17:51 -08:00
  • 659e0866f7 Upgrade from .vcd to .fst David Hunter 2024-11-16 20:17:28 -08:00
  • e4d21e9c2c Increase audio volume David Hunter 2024-11-16 18:40:49 -08:00
  • cdfb6e2cf7 Appease Quartus David Hunter 2024-11-16 17:57:33 -08:00
  • 95ce1b9aa0 Integrate uPD1771C to core, first pass David Hunter 2024-11-16 17:22:01 -08:00
  • 4ccd32372a upd1771c: Add clock enable David Hunter 2024-11-16 17:19:07 -08:00
  • 3379471e9d Implement inner carry bits and associated ADI ins. David Hunter 2024-11-16 14:57:37 -08:00
  • a85e5dc75a Fix ram_col[1] polarity David Hunter 2024-11-16 13:31:15 -08:00
  • 7ad38f6f76 Continuous sample output is working David Hunter 2024-11-16 13:02:10 -08:00
  • 5d8bc0d90a Implement OUT DA and PCM output David Hunter 2024-11-16 12:22:34 -08:00
  • 87a120ebd8 MUL and MIX are working David Hunter 2024-11-16 00:40:51 -08:00
  • d3a4075422 Tone interrupts are activated and called David Hunter 2024-11-14 23:32:49 -08:00
  • 530187ea5a Full packet received David Hunter 2024-11-10 23:30:48 -08:00
  • 63b1b4e273 First two bytes of packet received David Hunter 2024-11-10 22:55:06 -08:00