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#-----------------------------------------------------------
# Vivado v2016.3 (64-bit)
# SW Build 1682563 on Mon Oct 10 19:07:27 MDT 2016
# IP Build 1681267 on Mon Oct 10 21:28:31 MDT 2016
# Start of session at: Sat Dec 01 20:19:28 2018
# Process ID: 5944
# Current directory: C:/Users/bhayame/Desktop/Lab 7
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent3480 C:\Users\bhayame\Desktop\Lab 7\Lab 7.xpr
# Log file: C:/Users/bhayame/Desktop/Lab 7/vivado.log
# Journal file: C:/Users/bhayame/Desktop/Lab 7\vivado.jou
#-----------------------------------------------------------
start_gui
open_project {C:/Users/bhayame/Desktop/Lab 7/Lab 7.xpr}
Scanning sources...
Finished scanning sources
WARNING: [filemgmt 56-3] IP Output Repository Path: Could not find the directory 'C:/Users/bhayame/Desktop/Lab 7/Lab 7.cache/ip'.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2016.3/data/ip'.
open_project: Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 767.504 ; gain = 142.305
set_property source_mgmt_mode None [current_project]
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream
[Sat Dec 01 20:22:22 2018] Launched synth_1...
Run output will be captured here: C:/Users/bhayame/Desktop/Lab 7/Lab 7.runs/synth_1/runme.log
[Sat Dec 01 20:22:22 2018] Launched impl_1...
Run output will be captured here: C:/Users/bhayame/Desktop/Lab 7/Lab 7.runs/impl_1/runme.log
synth_design -rtl -name rtl_1
Command: synth_design -rtl -name rtl_1
Starting synth_design
Using part: xc7a35tcpg236-1
Top: TopLevel
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:01:07 ; elapsed = 00:03:02 . Memory (MB): peak = 818.484 ; gain = 605.527
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'TopLevel' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopLevel.v:23]
INFO: [Synth 8-638] synthesizing module 'TopStateMachine' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachine.v:23]
INFO: [Synth 8-638] synthesizing module 'TopStateMachineLogic' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachineLogic.v:23]
INFO: [Synth 8-256] done synthesizing module 'TopStateMachineLogic' (1#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachineLogic.v:23]
INFO: [Synth 8-638] synthesizing module 'FDRE' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b1
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE' (2#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
WARNING: [Synth 8-350] instance 'Q0_FF' of module 'FDRE' requires 5 connections, but only 4 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachine.v:45]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized0' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized0' (2#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
WARNING: [Synth 8-350] instance 'Q1_FF' of module 'FDRE' requires 5 connections, but only 4 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachine.v:46]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized1' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized1' (2#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
WARNING: [Synth 8-350] instance 'Q2_FF' of module 'FDRE' requires 5 connections, but only 4 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachine.v:47]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized2' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized2' (2#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
WARNING: [Synth 8-350] instance 'Q3_FF' of module 'FDRE' requires 5 connections, but only 4 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachine.v:48]
INFO: [Synth 8-256] done synthesizing module 'TopStateMachine' (3#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachine.v:23]
INFO: [Synth 8-638] synthesizing module 'LossDetector' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/LossDetector.v:23]
INFO: [Synth 8-256] done synthesizing module 'LossDetector' (4#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/LossDetector.v:23]
INFO: [Synth 8-638] synthesizing module 'WinDetector' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/WinDetector.v:23]
INFO: [Synth 8-256] done synthesizing module 'WinDetector' (5#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/WinDetector.v:23]
INFO: [Synth 8-638] synthesizing module 'lab7_clks' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Downloads/lab7_clks.v:24]
INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Downloads/lab7_clks.v:57]
INFO: [Synth 8-638] synthesizing module 'IBUF' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:14146]
Parameter CAPACITANCE bound to: DONT_CARE - type: string
Parameter IBUF_DELAY_VALUE bound to: 0 - type: string
Parameter IBUF_LOW_PWR bound to: TRUE - type: string
Parameter IFD_DELAY_VALUE bound to: AUTO - type: string
Parameter IOSTANDARD bound to: DEFAULT - type: string
INFO: [Synth 8-256] done synthesizing module 'IBUF' (6#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:14146]
INFO: [Synth 8-638] synthesizing module 'MMCME2_ADV' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:20414]
Parameter BANDWIDTH bound to: OPTIMIZED - type: string
Parameter CLKFBOUT_MULT_F bound to: 9.125000 - type: float
Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float
Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKIN1_PERIOD bound to: 10.000000 - type: float
Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float
Parameter CLKOUT0_DIVIDE_F bound to: 36.500000 - type: float
Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float
Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float
Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float
Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float
Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKOUT4_CASCADE bound to: FALSE - type: string
Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float
Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float
Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float
Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string
Parameter COMPENSATION bound to: ZHOLD - type: string
Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
Parameter IS_CLKINSEL_INVERTED bound to: 1'b0
Parameter IS_PSEN_INVERTED bound to: 1'b0
Parameter IS_PSINCDEC_INVERTED bound to: 1'b0
Parameter IS_PWRDWN_INVERTED bound to: 1'b0
Parameter IS_RST_INVERTED bound to: 1'b0
Parameter REF_JITTER1 bound to: 0.010000 - type: float
Parameter REF_JITTER2 bound to: 0.010000 - type: float
Parameter SS_EN bound to: FALSE - type: string
Parameter SS_MODE bound to: CENTER_HIGH - type: string
Parameter SS_MOD_PERIOD bound to: 10000 - type: integer
Parameter STARTUP_WAIT bound to: FALSE - type: string
INFO: [Synth 8-256] done synthesizing module 'MMCME2_ADV' (7#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:20414]
INFO: [Synth 8-638] synthesizing module 'BUFG' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:607]
INFO: [Synth 8-256] done synthesizing module 'BUFG' (8#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:607]
INFO: [Synth 8-256] done synthesizing module 'clk_wiz_0' (9#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Downloads/lab7_clks.v:57]
INFO: [Synth 8-638] synthesizing module 'clkcntrl4' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Downloads/lab7_clks.v:190]
INFO: [Synth 8-638] synthesizing module 'CB4CE_MXILINX_clkcntrl4' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Downloads/lab7_clks.v:306]
INFO: [Synth 8-638] synthesizing module 'FTCE_MXILINX_clkcntrl4' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Downloads/lab7_clks.v:276]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-638] synthesizing module 'XOR2' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:45290]
INFO: [Synth 8-256] done synthesizing module 'XOR2' (10#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:45290]
INFO: [Synth 8-638] synthesizing module 'FDCE' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3748]
Parameter INIT bound to: 1'b0
Parameter IS_CLR_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDCE' (11#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3748]
INFO: [Synth 8-256] done synthesizing module 'FTCE_MXILINX_clkcntrl4' (12#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Downloads/lab7_clks.v:276]
INFO: [Synth 8-638] synthesizing module 'AND4' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:108]
INFO: [Synth 8-256] done synthesizing module 'AND4' (13#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:108]
INFO: [Synth 8-638] synthesizing module 'AND3' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:60]
INFO: [Synth 8-256] done synthesizing module 'AND3' (14#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:60]
INFO: [Synth 8-638] synthesizing module 'AND2' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:14]
INFO: [Synth 8-256] done synthesizing module 'AND2' (15#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:14]
INFO: [Synth 8-638] synthesizing module 'VCC' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:44693]
INFO: [Synth 8-256] done synthesizing module 'VCC' (16#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:44693]
INFO: [Synth 8-256] done synthesizing module 'CB4CE_MXILINX_clkcntrl4' (17#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Downloads/lab7_clks.v:306]
INFO: [Synth 8-638] synthesizing module 'BUF' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:567]
INFO: [Synth 8-256] done synthesizing module 'BUF' (18#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:567]
WARNING: [Synth 8-3848] Net qsec in module/entity clkcntrl4 does not have driver. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Downloads/lab7_clks.v:194]
INFO: [Synth 8-256] done synthesizing module 'clkcntrl4' (19#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Downloads/lab7_clks.v:190]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Downloads/lab7_clks.v:40]
INFO: [Synth 8-638] synthesizing module 'STARTUPE2' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:43498]
Parameter PROG_USR bound to: FALSE - type: string
Parameter SIM_CCLK_FREQ bound to: 0.000000 - type: float
INFO: [Synth 8-256] done synthesizing module 'STARTUPE2' (20#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:43498]
INFO: [Synth 8-256] done synthesizing module 'lab7_clks' (21#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Downloads/lab7_clks.v:24]
WARNING: [Synth 8-350] instance 'not_so_slow' of module 'lab7_clks' requires 5 connections, but only 4 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopLevel.v:55]
INFO: [Synth 8-638] synthesizing module 'VGAController' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VGAController.v:23]
INFO: [Synth 8-638] synthesizing module 'HorizontalCounter' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizontalCounter.v:23]
INFO: [Synth 8-638] synthesizing module 'countU10' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/countU10.v:23]
INFO: [Synth 8-638] synthesizing module 'countU5' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/countU5.v:23]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized3' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized3' (21#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized4' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized4' (21#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized5' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized5' (21#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized6' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized6' (21#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized7' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized7' (21#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-256] done synthesizing module 'countU5' (22#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/countU5.v:23]
INFO: [Synth 8-256] done synthesizing module 'countU10' (23#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/countU10.v:23]
INFO: [Synth 8-256] done synthesizing module 'HorizontalCounter' (24#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizontalCounter.v:23]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized8' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized8' (24#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized9' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized9' (24#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'VerticalCounter' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VerticalCounter.v:23]
INFO: [Synth 8-256] done synthesizing module 'VerticalCounter' (25#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VerticalCounter.v:23]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized10' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized10' (25#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized11' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized11' (25#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'EdgeDetector' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/new/EdgeDetector.v:23]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized12' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized12' (25#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-256] done synthesizing module 'EdgeDetector' (26#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/new/EdgeDetector.v:23]
INFO: [Synth 8-256] done synthesizing module 'VGAController' (27#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VGAController.v:23]
INFO: [Synth 8-638] synthesizing module 'BorderGenerator' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BorderGenerator.v:23]
WARNING: [Synth 8-689] width (1) of port connection 'Q' does not match port width (10) of module 'countU10' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BorderGenerator.v:36]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BorderGenerator.v:36]
INFO: [Synth 8-638] synthesizing module 'FlashModule' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/FlashModule.v:23]
INFO: [Synth 8-256] done synthesizing module 'FlashModule' (28#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/FlashModule.v:23]
WARNING: [Synth 8-3848] Net SecOut in module/entity BorderGenerator does not have driver. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BorderGenerator.v:33]
INFO: [Synth 8-256] done synthesizing module 'BorderGenerator' (29#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BorderGenerator.v:23]
WARNING: [Synth 8-350] instance 'BorderGenerator' of module 'BorderGenerator' requires 6 connections, but only 5 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopLevel.v:60]
INFO: [Synth 8-638] synthesizing module 'SlugGenerator' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugGenerator.v:23]
WARNING: [Synth 8-689] width (1) of port connection 'Q' does not match port width (10) of module 'countU10' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugGenerator.v:43]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugGenerator.v:43]
INFO: [Synth 8-638] synthesizing module 'SlugPositionSet' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugPositionSet.v:23]
INFO: [Synth 8-256] done synthesizing module 'SlugPositionSet' (30#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugPositionSet.v:23]
INFO: [Synth 8-638] synthesizing module 'btnChecker' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/btnChecker.v:23]
INFO: [Synth 8-256] done synthesizing module 'btnChecker' (31#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/btnChecker.v:23]
INFO: [Synth 8-638] synthesizing module 'BGCollisionDetector' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BGCollisionDetector.v:23]
WARNING: [Synth 8-3848] Net DwStop in module/entity BGCollisionDetector does not have driver. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BGCollisionDetector.v:29]
WARNING: [Synth 8-3848] Net LeftStop in module/entity BGCollisionDetector does not have driver. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BGCollisionDetector.v:30]
WARNING: [Synth 8-3848] Net RightStop in module/entity BGCollisionDetector does not have driver. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BGCollisionDetector.v:31]
INFO: [Synth 8-256] done synthesizing module 'BGCollisionDetector' (32#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BGCollisionDetector.v:23]
INFO: [Synth 8-638] synthesizing module 'SlugVerticalComponent' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:23]
INFO: [Synth 8-638] synthesizing module 'countUD10L' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/countUD10L.v:23]
INFO: [Synth 8-638] synthesizing module 'countUD5L' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/new/countUD5L.v:23]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized13' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized13' (32#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized14' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized14' (32#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized15' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized15' (32#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized16' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized16' (32#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized17' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized17' (32#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'mux2to1' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/new/mux2to1.v:23]
INFO: [Synth 8-256] done synthesizing module 'mux2to1' (33#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/new/mux2to1.v:23]
INFO: [Synth 8-256] done synthesizing module 'countUD5L' (34#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/new/countUD5L.v:23]
WARNING: [Synth 8-350] instance 'counter2' of module 'countUD5L' requires 9 connections, but only 7 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/countUD10L.v:36]
INFO: [Synth 8-256] done synthesizing module 'countUD10L' (35#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/countUD10L.v:23]
WARNING: [Synth 8-350] instance 'counter0' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:35]
WARNING: [Synth 8-350] instance 'counter1' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:36]
WARNING: [Synth 8-350] instance 'counter2' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:37]
WARNING: [Synth 8-350] instance 'counter3' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:38]
WARNING: [Synth 8-350] instance 'counter4' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:39]
WARNING: [Synth 8-350] instance 'counter5' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:40]
WARNING: [Synth 8-350] instance 'counter6' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:41]
WARNING: [Synth 8-350] instance 'counter7' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:42]
WARNING: [Synth 8-350] instance 'counter8' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:43]
WARNING: [Synth 8-350] instance 'counter9' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:44]
WARNING: [Synth 8-350] instance 'counterA' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:45]
WARNING: [Synth 8-350] instance 'counterB' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:46]
WARNING: [Synth 8-350] instance 'counterC' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:47]
WARNING: [Synth 8-350] instance 'counterD' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:48]
WARNING: [Synth 8-350] instance 'counterE' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:49]
WARNING: [Synth 8-350] instance 'counterF' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:50]
INFO: [Synth 8-256] done synthesizing module 'SlugVerticalComponent' (36#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:23]
INFO: [Synth 8-638] synthesizing module 'SlugHorizontalComponent' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:23]
WARNING: [Synth 8-350] instance 'counter0' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:35]
WARNING: [Synth 8-350] instance 'counter1' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:36]
WARNING: [Synth 8-350] instance 'counter2' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:37]
WARNING: [Synth 8-350] instance 'counter3' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:38]
WARNING: [Synth 8-350] instance 'counter4' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:39]
WARNING: [Synth 8-350] instance 'counter5' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:40]
WARNING: [Synth 8-350] instance 'counter6' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:41]
WARNING: [Synth 8-350] instance 'counter7' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:42]
WARNING: [Synth 8-350] instance 'counter8' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:43]
WARNING: [Synth 8-350] instance 'counter9' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:44]
WARNING: [Synth 8-350] instance 'counterA' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:45]
WARNING: [Synth 8-350] instance 'counterB' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:46]
WARNING: [Synth 8-350] instance 'counterC' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:47]
WARNING: [Synth 8-350] instance 'counterD' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:48]
WARNING: [Synth 8-350] instance 'counterE' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:49]
WARNING: [Synth 8-350] instance 'counterF' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:50]
INFO: [Synth 8-256] done synthesizing module 'SlugHorizontalComponent' (37#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:23]
WARNING: [Synth 8-3848] Net SecOut in module/entity SlugGenerator does not have driver. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugGenerator.v:40]
INFO: [Synth 8-256] done synthesizing module 'SlugGenerator' (38#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugGenerator.v:23]
INFO: [Synth 8-638] synthesizing module 'VerticalObstacles' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VerticalObstacles.v:23]
INFO: [Synth 8-638] synthesizing module 'V1' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V1.v:23]
INFO: [Synth 8-256] done synthesizing module 'V1' (39#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V1.v:23]
INFO: [Synth 8-638] synthesizing module 'V2' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V2.v:23]
INFO: [Synth 8-256] done synthesizing module 'V2' (40#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V2.v:23]
INFO: [Synth 8-638] synthesizing module 'V3' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V3.v:23]
INFO: [Synth 8-256] done synthesizing module 'V3' (41#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V3.v:23]
INFO: [Synth 8-638] synthesizing module 'V4' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V4.v:23]
INFO: [Synth 8-256] done synthesizing module 'V4' (42#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V4.v:23]
INFO: [Synth 8-638] synthesizing module 'V5' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V5.v:23]
INFO: [Synth 8-256] done synthesizing module 'V5' (43#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V5.v:23]
INFO: [Synth 8-638] synthesizing module 'V6' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V6.v:23]
INFO: [Synth 8-256] done synthesizing module 'V6' (44#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V6.v:23]
INFO: [Synth 8-638] synthesizing module 'V7' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V7.v:23]
INFO: [Synth 8-256] done synthesizing module 'V7' (45#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V7.v:23]
INFO: [Synth 8-256] done synthesizing module 'VerticalObstacles' (46#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VerticalObstacles.v:23]
INFO: [Synth 8-638] synthesizing module 'VerticalGaps' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VerticalGaps.v:23]
INFO: [Synth 8-638] synthesizing module 'VertGap1' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap1.v:23]
INFO: [Synth 8-638] synthesizing module 'GapStateMachine' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapStateMachine.v:23]
INFO: [Synth 8-638] synthesizing module 'GapStateMachineLogic' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapStateMachineLogic.v:23]
INFO: [Synth 8-256] done synthesizing module 'GapStateMachineLogic' (47#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapStateMachineLogic.v:23]
WARNING: [Synth 8-350] instance 'Q0_FF' of module 'FDRE' requires 5 connections, but only 4 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapStateMachine.v:42]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized18' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized18' (47#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
WARNING: [Synth 8-350] instance 'Q1_FF' of module 'FDRE' requires 5 connections, but only 4 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapStateMachine.v:43]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized19' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized19' (47#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
WARNING: [Synth 8-350] instance 'Q2_FF' of module 'FDRE' requires 5 connections, but only 4 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapStateMachine.v:44]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized20' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized20' (47#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
WARNING: [Synth 8-350] instance 'Q3_FF' of module 'FDRE' requires 5 connections, but only 4 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapStateMachine.v:45]
INFO: [Synth 8-256] done synthesizing module 'GapStateMachine' (48#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapStateMachine.v:23]
INFO: [Synth 8-638] synthesizing module 'GapWallDetect' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapWallDetect.v:23]
INFO: [Synth 8-256] done synthesizing module 'GapWallDetect' (49#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapWallDetect.v:23]
INFO: [Synth 8-638] synthesizing module 'SlugRedDetect' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugRedDetect.v:23]
INFO: [Synth 8-256] done synthesizing module 'SlugRedDetect' (50#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugRedDetect.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap1.v:53]
INFO: [Synth 8-638] synthesizing module 'GapHorizontalComponent' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapHorizontalComponent.v:23]
INFO: [Synth 8-256] done synthesizing module 'GapHorizontalComponent' (51#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapHorizontalComponent.v:23]
INFO: [Synth 8-638] synthesizing module 'GapVerticalComponent' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapVerticalComponent.v:23]
INFO: [Synth 8-638] synthesizing module 'GapSize' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapSize.v:23]
INFO: [Synth 8-256] done synthesizing module 'GapSize' (52#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapSize.v:23]
INFO: [Synth 8-256] done synthesizing module 'GapVerticalComponent' (53#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapVerticalComponent.v:23]
INFO: [Synth 8-256] done synthesizing module 'VertGap1' (54#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap1.v:23]
INFO: [Synth 8-638] synthesizing module 'VertGap2' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap2.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap2.v:53]
INFO: [Synth 8-256] done synthesizing module 'VertGap2' (55#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap2.v:23]
INFO: [Synth 8-638] synthesizing module 'VertGap3' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap3.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap3.v:53]
INFO: [Synth 8-256] done synthesizing module 'VertGap3' (56#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap3.v:23]
INFO: [Synth 8-638] synthesizing module 'VertGap4' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap4.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap4.v:53]
INFO: [Synth 8-256] done synthesizing module 'VertGap4' (57#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap4.v:23]
INFO: [Synth 8-638] synthesizing module 'VertGap5' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap5.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap5.v:53]
INFO: [Synth 8-256] done synthesizing module 'VertGap5' (58#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap5.v:23]
INFO: [Synth 8-638] synthesizing module 'VertGap6' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap6.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap6.v:53]
INFO: [Synth 8-256] done synthesizing module 'VertGap6' (59#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap6.v:23]
INFO: [Synth 8-638] synthesizing module 'VertGap7' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap7.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap7.v:53]
INFO: [Synth 8-256] done synthesizing module 'VertGap7' (60#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap7.v:23]
INFO: [Synth 8-256] done synthesizing module 'VerticalGaps' (61#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VerticalGaps.v:23]
WARNING: [Synth 8-350] instance 'VerticalGaps' of module 'VerticalGaps' requires 12 connections, but only 11 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopLevel.v:66]
INFO: [Synth 8-638] synthesizing module 'HorizontalObstacles' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizontalObstacles.v:23]
INFO: [Synth 8-638] synthesizing module 'H1' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H1.v:23]
INFO: [Synth 8-256] done synthesizing module 'H1' (62#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H1.v:23]
INFO: [Synth 8-638] synthesizing module 'H2' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H2.v:23]
INFO: [Synth 8-256] done synthesizing module 'H2' (63#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H2.v:23]
INFO: [Synth 8-638] synthesizing module 'H3' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H3.v:23]
INFO: [Synth 8-256] done synthesizing module 'H3' (64#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H3.v:23]
INFO: [Synth 8-638] synthesizing module 'H4' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H4.v:23]
INFO: [Synth 8-256] done synthesizing module 'H4' (65#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H4.v:23]
INFO: [Synth 8-638] synthesizing module 'H5' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H5.v:23]
INFO: [Synth 8-256] done synthesizing module 'H5' (66#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H5.v:23]
INFO: [Synth 8-638] synthesizing module 'H6' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H6.v:23]
INFO: [Synth 8-256] done synthesizing module 'H6' (67#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H6.v:23]
INFO: [Synth 8-638] synthesizing module 'H7' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H7.v:23]
INFO: [Synth 8-256] done synthesizing module 'H7' (68#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H7.v:23]
INFO: [Synth 8-256] done synthesizing module 'HorizontalObstacles' (69#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizontalObstacles.v:23]
INFO: [Synth 8-638] synthesizing module 'HorizontalGaps' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizontalGaps.v:23]
INFO: [Synth 8-638] synthesizing module 'HorizGap1' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap1.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap1.v:53]
INFO: [Synth 8-256] done synthesizing module 'HorizGap1' (70#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap1.v:23]
INFO: [Synth 8-638] synthesizing module 'HorizGap2' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap2.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap2.v:53]
INFO: [Synth 8-256] done synthesizing module 'HorizGap2' (71#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap2.v:23]
INFO: [Synth 8-638] synthesizing module 'HorizGap3' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap3.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap3.v:53]
INFO: [Synth 8-256] done synthesizing module 'HorizGap3' (72#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap3.v:23]
INFO: [Synth 8-638] synthesizing module 'HorizGap4' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap4.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap4.v:53]
INFO: [Synth 8-256] done synthesizing module 'HorizGap4' (73#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap4.v:23]
INFO: [Synth 8-638] synthesizing module 'HorizGap5' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap5.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap5.v:53]
INFO: [Synth 8-256] done synthesizing module 'HorizGap5' (74#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap5.v:23]
INFO: [Synth 8-638] synthesizing module 'HorizGap6' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap6.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap6.v:53]
INFO: [Synth 8-256] done synthesizing module 'HorizGap6' (75#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap6.v:23]
INFO: [Synth 8-638] synthesizing module 'HorizGap7' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap7.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap7.v:53]
INFO: [Synth 8-256] done synthesizing module 'HorizGap7' (76#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap7.v:23]
INFO: [Synth 8-256] done synthesizing module 'HorizontalGaps' (77#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizontalGaps.v:23]
WARNING: [Synth 8-350] instance 'HorizontalGaps' of module 'HorizontalGaps' requires 12 connections, but only 11 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopLevel.v:70]
INFO: [Synth 8-638] synthesizing module 'qsecTicker' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/qsecTicker.v:23]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized21' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized21' (77#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized22' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized22' (77#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized23' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized23' (77#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized24' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized24' (77#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized25' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized25' (77#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-256] done synthesizing module 'qsecTicker' (78#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/qsecTicker.v:23]
INFO: [Synth 8-638] synthesizing module 'Timer' [C:/Users/bhayame/Desktop/TIMER/TIMER.srcs/sources_1/new/Timer.v:20]
INFO: [Synth 8-638] synthesizing module 'secondTicker' [C:/Users/bhayame/Desktop/TIMER/TIMER.srcs/sources_1/new/secondTicker.v:23]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized26' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized26' (78#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized27' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized27' (78#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized28' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized28' (78#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized29' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized29' (78#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized30' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized30' (78#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized31' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized31' (78#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-256] done synthesizing module 'secondTicker' (79#1) [C:/Users/bhayame/Desktop/TIMER/TIMER.srcs/sources_1/new/secondTicker.v:23]
INFO: [Synth 8-638] synthesizing module 'countU4' [C:/Users/bhayame/Desktop/TIMER/TIMER.srcs/sources_1/new/countU4.v:23]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized32' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized32' (79#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized33' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized33' (79#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized34' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized34' (79#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized35' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized35' (79#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-256] done synthesizing module 'countU4' (80#1) [C:/Users/bhayame/Desktop/TIMER/TIMER.srcs/sources_1/new/countU4.v:23]
INFO: [Synth 8-638] synthesizing module 'countU3' [C:/Users/bhayame/Desktop/TIMER/TIMER.srcs/sources_1/new/countU3.v:23]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized36' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized36' (80#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized37' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized37' (80#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized38' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized38' (80#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-256] done synthesizing module 'countU3' (81#1) [C:/Users/bhayame/Desktop/TIMER/TIMER.srcs/sources_1/new/countU3.v:23]
INFO: [Synth 8-256] done synthesizing module 'Timer' (82#1) [C:/Users/bhayame/Desktop/TIMER/TIMER.srcs/sources_1/new/Timer.v:20]
INFO: [Synth 8-638] synthesizing module 'RingCounter' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Desktop/Lab 4/Lab 4.srcs/sources_1/new/RingCounter.v:23]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized39' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized39' (82#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized40' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized40' (82#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized41' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized41' (82#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
WARNING: [Synth 8-3848] Net reset in module/entity RingCounter does not have driver. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Desktop/Lab 4/Lab 4.srcs/sources_1/new/RingCounter.v:29]
INFO: [Synth 8-256] done synthesizing module 'RingCounter' (83#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Desktop/Lab 4/Lab 4.srcs/sources_1/new/RingCounter.v:23]
INFO: [Synth 8-638] synthesizing module 'Selector' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Desktop/Lab 4/Lab 4.srcs/sources_1/new/Selector.v:23]
INFO: [Synth 8-256] done synthesizing module 'Selector' (84#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Desktop/Lab 4/Lab 4.srcs/sources_1/new/Selector.v:23]
INFO: [Synth 8-638] synthesizing module 'hex7seg' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Desktop/Lab 4/Lab 4.srcs/sources_1/new/hex7seg.v:23]
INFO: [Synth 8-638] synthesizing module 'm8_1e' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/new/m8_1e.v:23]
INFO: [Synth 8-256] done synthesizing module 'm8_1e' (85#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/new/m8_1e.v:23]
INFO: [Synth 8-256] done synthesizing module 'hex7seg' (86#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Desktop/Lab 4/Lab 4.srcs/sources_1/new/hex7seg.v:23]
INFO: [Synth 8-256] done synthesizing module 'TopLevel' (87#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopLevel.v:23]
WARNING: [Synth 8-3917] design TopLevel has port led[15] driven by constant 0
WARNING: [Synth 8-3917] design TopLevel has port led[14] driven by constant 0
WARNING: [Synth 8-3917] design TopLevel has port led[13] driven by constant 0
WARNING: [Synth 8-3917] design TopLevel has port led[12] driven by constant 0
WARNING: [Synth 8-3917] design TopLevel has port led[11] driven by constant 0
WARNING: [Synth 8-3917] design TopLevel has port led[10] driven by constant 0
WARNING: [Synth 8-3917] design TopLevel has port led[9] driven by constant 0
WARNING: [Synth 8-3917] design TopLevel has port led[4] driven by constant 0
WARNING: [Synth 8-3331] design HorizGap7 has unconnected port reset
WARNING: [Synth 8-3331] design HorizGap6 has unconnected port reset
WARNING: [Synth 8-3331] design HorizGap5 has unconnected port reset
WARNING: [Synth 8-3331] design HorizGap4 has unconnected port reset
WARNING: [Synth 8-3331] design HorizGap3 has unconnected port reset
WARNING: [Synth 8-3331] design HorizGap2 has unconnected port reset
WARNING: [Synth 8-3331] design HorizGap1 has unconnected port reset
WARNING: [Synth 8-3331] design H7 has unconnected port Hcount[2]
WARNING: [Synth 8-3331] design H7 has unconnected port Hcount[1]
WARNING: [Synth 8-3331] design H7 has unconnected port Hcount[0]
WARNING: [Synth 8-3331] design H6 has unconnected port Hcount[2]
WARNING: [Synth 8-3331] design H6 has unconnected port Hcount[1]
WARNING: [Synth 8-3331] design H6 has unconnected port Hcount[0]
WARNING: [Synth 8-3331] design H5 has unconnected port Hcount[2]
WARNING: [Synth 8-3331] design H5 has unconnected port Hcount[1]
WARNING: [Synth 8-3331] design H5 has unconnected port Hcount[0]
WARNING: [Synth 8-3331] design H4 has unconnected port Hcount[2]
WARNING: [Synth 8-3331] design H4 has unconnected port Hcount[1]
WARNING: [Synth 8-3331] design H4 has unconnected port Hcount[0]
WARNING: [Synth 8-3331] design H3 has unconnected port Hcount[2]
WARNING: [Synth 8-3331] design H3 has unconnected port Hcount[1]
WARNING: [Synth 8-3331] design H3 has unconnected port Hcount[0]
WARNING: [Synth 8-3331] design H2 has unconnected port Hcount[2]
WARNING: [Synth 8-3331] design H2 has unconnected port Hcount[1]
WARNING: [Synth 8-3331] design H2 has unconnected port Hcount[0]
WARNING: [Synth 8-3331] design H1 has unconnected port Hcount[2]
WARNING: [Synth 8-3331] design H1 has unconnected port Hcount[1]
WARNING: [Synth 8-3331] design H1 has unconnected port Hcount[0]
WARNING: [Synth 8-3331] design VertGap7 has unconnected port reset
WARNING: [Synth 8-3331] design VertGap6 has unconnected port reset
WARNING: [Synth 8-3331] design VertGap5 has unconnected port reset
WARNING: [Synth 8-3331] design VertGap4 has unconnected port reset
WARNING: [Synth 8-3331] design VertGap3 has unconnected port reset
WARNING: [Synth 8-3331] design VertGap2 has unconnected port reset
WARNING: [Synth 8-3331] design VertGap1 has unconnected port reset
WARNING: [Synth 8-3331] design V7 has unconnected port Vcount[2]
WARNING: [Synth 8-3331] design V7 has unconnected port Vcount[1]
WARNING: [Synth 8-3331] design V7 has unconnected port Vcount[0]
WARNING: [Synth 8-3331] design V6 has unconnected port Vcount[2]
WARNING: [Synth 8-3331] design V6 has unconnected port Vcount[1]
WARNING: [Synth 8-3331] design V6 has unconnected port Vcount[0]
WARNING: [Synth 8-3331] design V5 has unconnected port Vcount[2]
WARNING: [Synth 8-3331] design V5 has unconnected port Vcount[1]
WARNING: [Synth 8-3331] design V5 has unconnected port Vcount[0]
WARNING: [Synth 8-3331] design V4 has unconnected port Vcount[2]
WARNING: [Synth 8-3331] design V4 has unconnected port Vcount[1]
WARNING: [Synth 8-3331] design V4 has unconnected port Vcount[0]
WARNING: [Synth 8-3331] design V3 has unconnected port Vcount[2]
WARNING: [Synth 8-3331] design V3 has unconnected port Vcount[1]
WARNING: [Synth 8-3331] design V3 has unconnected port Vcount[0]
WARNING: [Synth 8-3331] design V2 has unconnected port Vcount[2]
WARNING: [Synth 8-3331] design V2 has unconnected port Vcount[1]
WARNING: [Synth 8-3331] design V2 has unconnected port Vcount[0]
WARNING: [Synth 8-3331] design V1 has unconnected port Vcount[2]
WARNING: [Synth 8-3331] design V1 has unconnected port Vcount[1]
WARNING: [Synth 8-3331] design V1 has unconnected port Vcount[0]
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port DwStop
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port LeftStop
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port RightStop
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port Hcount[9]
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port Hcount[8]
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port Hcount[7]
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port Hcount[6]
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port Hcount[5]
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port Hcount[4]
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port Hcount[3]
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port Hcount[2]
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port Hcount[1]
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port Hcount[0]
WARNING: [Synth 8-3331] design SlugPositionSet has unconnected port Hcount[0]
WARNING: [Synth 8-3331] design BorderGenerator has unconnected port Hcount[2]
WARNING: [Synth 8-3331] design BorderGenerator has unconnected port Hcount[1]
WARNING: [Synth 8-3331] design BorderGenerator has unconnected port Hcount[0]
WARNING: [Synth 8-3331] design BorderGenerator has unconnected port Vcount[2]
WARNING: [Synth 8-3331] design BorderGenerator has unconnected port Vcount[1]
WARNING: [Synth 8-3331] design BorderGenerator has unconnected port Vcount[0]
WARNING: [Synth 8-3331] design clkcntrl4 has unconnected port qsec
WARNING: [Synth 8-3331] design TopStateMachineLogic has unconnected port clk
WARNING: [Synth 8-3331] design TopLevel has unconnected port sw[15]
WARNING: [Synth 8-3331] design TopLevel has unconnected port sw[14]
WARNING: [Synth 8-3331] design TopLevel has unconnected port sw[13]
WARNING: [Synth 8-3331] design TopLevel has unconnected port sw[12]
WARNING: [Synth 8-3331] design TopLevel has unconnected port sw[11]
WARNING: [Synth 8-3331] design TopLevel has unconnected port sw[10]
WARNING: [Synth 8-3331] design TopLevel has unconnected port sw[9]
WARNING: [Synth 8-3331] design TopLevel has unconnected port sw[8]
WARNING: [Synth 8-3331] design TopLevel has unconnected port sw[7]
WARNING: [Synth 8-3331] design TopLevel has unconnected port sw[3]
WARNING: [Synth 8-3331] design TopLevel has unconnected port sw[2]
WARNING: [Synth 8-3331] design TopLevel has unconnected port sw[1]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:01:09 ; elapsed = 00:03:05 . Memory (MB): peak = 863.488 ; gain = 650.531
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
WARNING: [Synth 8-3295] tying undriven pin Q0_FF:R to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachine.v:45]
WARNING: [Synth 8-3295] tying undriven pin Q1_FF:R to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachine.v:46]
WARNING: [Synth 8-3295] tying undriven pin Q2_FF:R to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachine.v:47]
WARNING: [Synth 8-3295] tying undriven pin Q3_FF:R to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachine.v:48]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BorderGenerator.v:36]
WARNING: [Synth 8-3295] tying undriven pin FlashModule:sec to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BorderGenerator.v:37]
WARNING: [Synth 8-3295] tying undriven pin counter0:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:35]
WARNING: [Synth 8-3295] tying undriven pin counter1:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:36]
WARNING: [Synth 8-3295] tying undriven pin counter2:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:37]
WARNING: [Synth 8-3295] tying undriven pin counter3:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:38]
WARNING: [Synth 8-3295] tying undriven pin counter4:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:39]
WARNING: [Synth 8-3295] tying undriven pin counter5:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:40]
WARNING: [Synth 8-3295] tying undriven pin counter6:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:41]
WARNING: [Synth 8-3295] tying undriven pin counter7:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:42]
WARNING: [Synth 8-3295] tying undriven pin counter8:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:43]
WARNING: [Synth 8-3295] tying undriven pin counter9:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:44]
WARNING: [Synth 8-3295] tying undriven pin counterA:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:45]
WARNING: [Synth 8-3295] tying undriven pin counterB:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:46]
WARNING: [Synth 8-3295] tying undriven pin counterC:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:47]
WARNING: [Synth 8-3295] tying undriven pin counterD:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:48]
WARNING: [Synth 8-3295] tying undriven pin counterE:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:49]
WARNING: [Synth 8-3295] tying undriven pin counterF:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:50]
WARNING: [Synth 8-3295] tying undriven pin counter0:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:35]
WARNING: [Synth 8-3295] tying undriven pin counter1:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:36]
WARNING: [Synth 8-3295] tying undriven pin counter2:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:37]
WARNING: [Synth 8-3295] tying undriven pin counter3:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:38]
WARNING: [Synth 8-3295] tying undriven pin counter4:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:39]
WARNING: [Synth 8-3295] tying undriven pin counter5:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:40]
WARNING: [Synth 8-3295] tying undriven pin counter6:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:41]
WARNING: [Synth 8-3295] tying undriven pin counter7:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:42]
WARNING: [Synth 8-3295] tying undriven pin counter8:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:43]
WARNING: [Synth 8-3295] tying undriven pin counter9:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:44]
WARNING: [Synth 8-3295] tying undriven pin counterA:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:45]
WARNING: [Synth 8-3295] tying undriven pin counterB:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:46]
WARNING: [Synth 8-3295] tying undriven pin counterC:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:47]
WARNING: [Synth 8-3295] tying undriven pin counterD:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:48]
WARNING: [Synth 8-3295] tying undriven pin counterE:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:49]
WARNING: [Synth 8-3295] tying undriven pin counterF:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:50]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugGenerator.v:43]
WARNING: [Synth 8-3295] tying undriven pin FlashModule:sec to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugGenerator.v:44]
WARNING: [Synth 8-3295] tying undriven pin Q0_FF:R to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapStateMachine.v:42]
WARNING: [Synth 8-3295] tying undriven pin Q1_FF:R to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapStateMachine.v:43]
WARNING: [Synth 8-3295] tying undriven pin Q2_FF:R to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapStateMachine.v:44]
WARNING: [Synth 8-3295] tying undriven pin Q3_FF:R to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapStateMachine.v:45]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap1.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap2.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap3.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap4.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap5.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap6.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap7.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap1.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap2.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap3.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap4.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap5.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap6.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap7.v:53]
WARNING: [Synth 8-3295] tying undriven pin ff0:R to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Desktop/Lab 4/Lab 4.srcs/sources_1/new/RingCounter.v:29]
WARNING: [Synth 8-3295] tying undriven pin ff1:R to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Desktop/Lab 4/Lab 4.srcs/sources_1/new/RingCounter.v:30]
WARNING: [Synth 8-3295] tying undriven pin ff2:R to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Desktop/Lab 4/Lab 4.srcs/sources_1/new/RingCounter.v:31]
WARNING: [Synth 8-3295] tying undriven pin ff3:R to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Desktop/Lab 4/Lab 4.srcs/sources_1/new/RingCounter.v:32]
WARNING: [Synth 8-3295] tying undriven pin BorderGenerator:clk to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopLevel.v:60]
WARNING: [Synth 8-3295] tying undriven pin VerticalGaps:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopLevel.v:66]
WARNING: [Synth 8-3295] tying undriven pin HorizontalGaps:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopLevel.v:70]
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:01:10 ; elapsed = 00:03:05 . Memory (MB): peak = 863.488 ; gain = 650.531
---------------------------------------------------------------------------------
INFO: [Netlist 29-17] Analyzing 52 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-140] Inserted 1 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 14 OBUFs to IO ports without IO buffers.
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/constrs_1/imports/Desktop/Basys3_Master.xdc]
Finished Parsing XDC File [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/constrs_1/imports/Desktop/Basys3_Master.xdc]
Completed Processing XDC Constraints
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 49 instances were transformed.
AND2 => LUT2: 12 instances
AND3 => LUT3: 6 instances
AND4 => LUT4: 6 instances
BUF => LUT1: 1 instances
XOR2 => LUT2: 24 instances
RTL Elaboration Complete: : Time (s): cpu = 00:01:30 ; elapsed = 00:03:25 . Memory (MB): peak = 1177.059 ; gain = 964.102
266 Infos, 234 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 1177.059 ; gain = 393.371
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:
****** Xilinx hw_server v2016.3
**** Build date : Oct 10 2016-19:47:06
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
connect_hw_server: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1182.895 ; gain = 0.000
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210183A28396A
set_property PROGRAM.FILE {C:/Users/bhayame/Desktop/Lab 7/Lab 7.runs/impl_1/TopLevel.bit} [lindex [get_hw_devices xc7a35t_0] 0]
current_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
set_property PROGRAM.FILE {C:/Users/bhayame/Desktop/Lab 7/Lab 7.runs/impl_1/TopLevel.bit} [lindex [get_hw_devices xc7a35t_0] 0]
program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream
[Sat Dec 01 20:28:44 2018] Launched synth_1...
Run output will be captured here: C:/Users/bhayame/Desktop/Lab 7/Lab 7.runs/synth_1/runme.log
[Sat Dec 01 20:28:44 2018] Launched impl_1...
Run output will be captured here: C:/Users/bhayame/Desktop/Lab 7/Lab 7.runs/impl_1/runme.log
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BorderGenerator.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachineLogic.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/qsecTicker.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugGenerator.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [C:/Users/bhayame/Desktop/TIMER/TIMER.srcs/sources_1/new/countU3.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [C:/Users/bhayame/Desktop/TIMER/TIMER.srcs/sources_1/new/countU4.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/new/EdgeDetector.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachine.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [C:/Users/bhayame/Desktop/TIMER/TIMER.srcs/sources_1/new/Timer.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopLevel.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BorderGenerator.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachineLogic.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/qsecTicker.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugGenerator.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [C:/Users/bhayame/Desktop/TIMER/TIMER.srcs/sources_1/new/countU3.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [C:/Users/bhayame/Desktop/TIMER/TIMER.srcs/sources_1/new/countU4.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/new/EdgeDetector.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachine.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [C:/Users/bhayame/Desktop/TIMER/TIMER.srcs/sources_1/new/Timer.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopLevel.v:]
ERROR: [Common 17-180] Spawn failed: No error
set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
set_property PROGRAM.FILE {C:/Users/bhayame/Desktop/Lab 7/Lab 7.runs/impl_1/TopLevel.bit} [lindex [get_hw_devices xc7a35t_0] 0]
program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
reset_run synth_1
launch_runs impl_1
[Sat Dec 01 20:36:19 2018] Launched synth_1...
Run output will be captured here: C:/Users/bhayame/Desktop/Lab 7/Lab 7.runs/synth_1/runme.log
[Sat Dec 01 20:36:19 2018] Launched impl_1...
Run output will be captured here: C:/Users/bhayame/Desktop/Lab 7/Lab 7.runs/impl_1/runme.log
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream
[Sat Dec 01 20:41:02 2018] Launched synth_1...
Run output will be captured here: C:/Users/bhayame/Desktop/Lab 7/Lab 7.runs/synth_1/runme.log
[Sat Dec 01 20:41:02 2018] Launched impl_1...
Run output will be captured here: C:/Users/bhayame/Desktop/Lab 7/Lab 7.runs/impl_1/runme.log
set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
set_property PROGRAM.FILE {C:/Users/bhayame/Desktop/Lab 7/Lab 7.runs/impl_1/TopLevel.bit} [lindex [get_hw_devices xc7a35t_0] 0]
program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream
[Sat Dec 01 20:49:21 2018] Launched synth_1...
Run output will be captured here: C:/Users/bhayame/Desktop/Lab 7/Lab 7.runs/synth_1/runme.log
[Sat Dec 01 20:49:21 2018] Launched impl_1...
Run output will be captured here: C:/Users/bhayame/Desktop/Lab 7/Lab 7.runs/impl_1/runme.log
reset_run synth_1
launch_runs impl_1
[Sat Dec 01 20:50:09 2018] Launched synth_1...
Run output will be captured here: C:/Users/bhayame/Desktop/Lab 7/Lab 7.runs/synth_1/runme.log
[Sat Dec 01 20:50:09 2018] Launched impl_1...
Run output will be captured here: C:/Users/bhayame/Desktop/Lab 7/Lab 7.runs/impl_1/runme.log
refresh_design
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:04:05 ; elapsed = 00:33:19 . Memory (MB): peak = 1296.773 ; gain = 1083.816
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'TopLevel' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopLevel.v:23]
INFO: [Synth 8-638] synthesizing module 'TopStateMachine' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachine.v:23]
INFO: [Synth 8-638] synthesizing module 'TopStateMachineLogic' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachineLogic.v:23]
INFO: [Synth 8-256] done synthesizing module 'TopStateMachineLogic' (1#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachineLogic.v:23]
INFO: [Synth 8-638] synthesizing module 'FDRE' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b1
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE' (2#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
WARNING: [Synth 8-350] instance 'Q0_FF' of module 'FDRE' requires 5 connections, but only 4 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachine.v:45]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized0' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized0' (2#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
WARNING: [Synth 8-350] instance 'Q1_FF' of module 'FDRE' requires 5 connections, but only 4 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachine.v:46]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized1' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized1' (2#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
WARNING: [Synth 8-350] instance 'Q2_FF' of module 'FDRE' requires 5 connections, but only 4 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachine.v:47]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized2' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized2' (2#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
WARNING: [Synth 8-350] instance 'Q3_FF' of module 'FDRE' requires 5 connections, but only 4 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachine.v:48]
INFO: [Synth 8-256] done synthesizing module 'TopStateMachine' (3#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachine.v:23]
INFO: [Synth 8-638] synthesizing module 'LossDetector' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/LossDetector.v:23]
INFO: [Synth 8-256] done synthesizing module 'LossDetector' (4#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/LossDetector.v:23]
INFO: [Synth 8-638] synthesizing module 'WinDetector' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/WinDetector.v:23]
INFO: [Synth 8-256] done synthesizing module 'WinDetector' (5#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/WinDetector.v:23]
INFO: [Synth 8-638] synthesizing module 'lab7_clks' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Downloads/lab7_clks.v:24]
INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Downloads/lab7_clks.v:57]
INFO: [Synth 8-638] synthesizing module 'IBUF' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:14146]
Parameter CAPACITANCE bound to: DONT_CARE - type: string
Parameter IBUF_DELAY_VALUE bound to: 0 - type: string
Parameter IBUF_LOW_PWR bound to: TRUE - type: string
Parameter IFD_DELAY_VALUE bound to: AUTO - type: string
Parameter IOSTANDARD bound to: DEFAULT - type: string
INFO: [Synth 8-256] done synthesizing module 'IBUF' (6#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:14146]
INFO: [Synth 8-638] synthesizing module 'MMCME2_ADV' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:20414]
Parameter BANDWIDTH bound to: OPTIMIZED - type: string
Parameter CLKFBOUT_MULT_F bound to: 9.125000 - type: float
Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float
Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKIN1_PERIOD bound to: 10.000000 - type: float
Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float
Parameter CLKOUT0_DIVIDE_F bound to: 36.500000 - type: float
Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float
Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float
Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float
Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float
Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKOUT4_CASCADE bound to: FALSE - type: string
Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float
Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float
Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float
Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string
Parameter COMPENSATION bound to: ZHOLD - type: string
Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
Parameter IS_CLKINSEL_INVERTED bound to: 1'b0
Parameter IS_PSEN_INVERTED bound to: 1'b0
Parameter IS_PSINCDEC_INVERTED bound to: 1'b0
Parameter IS_PWRDWN_INVERTED bound to: 1'b0
Parameter IS_RST_INVERTED bound to: 1'b0
Parameter REF_JITTER1 bound to: 0.010000 - type: float
Parameter REF_JITTER2 bound to: 0.010000 - type: float
Parameter SS_EN bound to: FALSE - type: string
Parameter SS_MODE bound to: CENTER_HIGH - type: string
Parameter SS_MOD_PERIOD bound to: 10000 - type: integer
Parameter STARTUP_WAIT bound to: FALSE - type: string
INFO: [Synth 8-256] done synthesizing module 'MMCME2_ADV' (7#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:20414]
INFO: [Synth 8-638] synthesizing module 'BUFG' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:607]
INFO: [Synth 8-256] done synthesizing module 'BUFG' (8#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:607]
INFO: [Synth 8-256] done synthesizing module 'clk_wiz_0' (9#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Downloads/lab7_clks.v:57]
INFO: [Synth 8-638] synthesizing module 'clkcntrl4' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Downloads/lab7_clks.v:190]
INFO: [Synth 8-638] synthesizing module 'CB4CE_MXILINX_clkcntrl4' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Downloads/lab7_clks.v:306]
INFO: [Synth 8-638] synthesizing module 'FTCE_MXILINX_clkcntrl4' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Downloads/lab7_clks.v:276]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-638] synthesizing module 'XOR2' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:45290]
INFO: [Synth 8-256] done synthesizing module 'XOR2' (10#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:45290]
INFO: [Synth 8-638] synthesizing module 'FDCE' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3748]
Parameter INIT bound to: 1'b0
Parameter IS_CLR_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDCE' (11#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3748]
INFO: [Synth 8-256] done synthesizing module 'FTCE_MXILINX_clkcntrl4' (12#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Downloads/lab7_clks.v:276]
INFO: [Synth 8-638] synthesizing module 'AND4' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:108]
INFO: [Synth 8-256] done synthesizing module 'AND4' (13#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:108]
INFO: [Synth 8-638] synthesizing module 'AND3' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:60]
INFO: [Synth 8-256] done synthesizing module 'AND3' (14#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:60]
INFO: [Synth 8-638] synthesizing module 'AND2' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:14]
INFO: [Synth 8-256] done synthesizing module 'AND2' (15#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:14]
INFO: [Synth 8-638] synthesizing module 'VCC' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:44693]
INFO: [Synth 8-256] done synthesizing module 'VCC' (16#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:44693]
INFO: [Synth 8-256] done synthesizing module 'CB4CE_MXILINX_clkcntrl4' (17#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Downloads/lab7_clks.v:306]
INFO: [Synth 8-638] synthesizing module 'BUF' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:567]
INFO: [Synth 8-256] done synthesizing module 'BUF' (18#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:567]
WARNING: [Synth 8-3848] Net qsec in module/entity clkcntrl4 does not have driver. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Downloads/lab7_clks.v:194]
INFO: [Synth 8-256] done synthesizing module 'clkcntrl4' (19#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Downloads/lab7_clks.v:190]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Downloads/lab7_clks.v:40]
INFO: [Synth 8-638] synthesizing module 'STARTUPE2' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:43498]
Parameter PROG_USR bound to: FALSE - type: string
Parameter SIM_CCLK_FREQ bound to: 0.000000 - type: float
INFO: [Synth 8-256] done synthesizing module 'STARTUPE2' (20#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:43498]
INFO: [Synth 8-256] done synthesizing module 'lab7_clks' (21#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Downloads/lab7_clks.v:24]
WARNING: [Synth 8-350] instance 'not_so_slow' of module 'lab7_clks' requires 5 connections, but only 4 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopLevel.v:57]
INFO: [Synth 8-638] synthesizing module 'VGAController' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VGAController.v:23]
INFO: [Synth 8-638] synthesizing module 'HorizontalCounter' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizontalCounter.v:23]
INFO: [Synth 8-638] synthesizing module 'countU10' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/countU10.v:23]
INFO: [Synth 8-638] synthesizing module 'countU5' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/countU5.v:23]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized3' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized3' (21#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized4' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized4' (21#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized5' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized5' (21#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized6' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized6' (21#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized7' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized7' (21#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-256] done synthesizing module 'countU5' (22#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/countU5.v:23]
INFO: [Synth 8-256] done synthesizing module 'countU10' (23#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/countU10.v:23]
INFO: [Synth 8-256] done synthesizing module 'HorizontalCounter' (24#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizontalCounter.v:23]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized8' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized8' (24#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized9' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized9' (24#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'VerticalCounter' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VerticalCounter.v:23]
INFO: [Synth 8-256] done synthesizing module 'VerticalCounter' (25#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VerticalCounter.v:23]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized10' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized10' (25#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized11' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized11' (25#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'EdgeDetector' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/new/EdgeDetector.v:23]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized12' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized12' (25#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-256] done synthesizing module 'EdgeDetector' (26#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/new/EdgeDetector.v:23]
INFO: [Synth 8-256] done synthesizing module 'VGAController' (27#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VGAController.v:23]
INFO: [Synth 8-638] synthesizing module 'BorderGenerator' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BorderGenerator.v:23]
WARNING: [Synth 8-689] width (1) of port connection 'Q' does not match port width (10) of module 'countU10' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BorderGenerator.v:36]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BorderGenerator.v:36]
INFO: [Synth 8-638] synthesizing module 'FlashModule' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/FlashModule.v:23]
INFO: [Synth 8-256] done synthesizing module 'FlashModule' (28#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/FlashModule.v:23]
WARNING: [Synth 8-3848] Net SecOut in module/entity BorderGenerator does not have driver. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BorderGenerator.v:33]
INFO: [Synth 8-256] done synthesizing module 'BorderGenerator' (29#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BorderGenerator.v:23]
WARNING: [Synth 8-350] instance 'BorderGenerator' of module 'BorderGenerator' requires 6 connections, but only 5 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopLevel.v:62]
INFO: [Synth 8-638] synthesizing module 'SlugGenerator' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugGenerator.v:23]
WARNING: [Synth 8-689] width (1) of port connection 'Q' does not match port width (10) of module 'countU10' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugGenerator.v:43]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugGenerator.v:43]
INFO: [Synth 8-638] synthesizing module 'SlugPositionSet' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugPositionSet.v:23]
INFO: [Synth 8-256] done synthesizing module 'SlugPositionSet' (30#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugPositionSet.v:23]
INFO: [Synth 8-638] synthesizing module 'btnChecker' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/btnChecker.v:23]
INFO: [Synth 8-256] done synthesizing module 'btnChecker' (31#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/btnChecker.v:23]
INFO: [Synth 8-638] synthesizing module 'BGCollisionDetector' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BGCollisionDetector.v:23]
WARNING: [Synth 8-3848] Net DwStop in module/entity BGCollisionDetector does not have driver. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BGCollisionDetector.v:29]
WARNING: [Synth 8-3848] Net LeftStop in module/entity BGCollisionDetector does not have driver. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BGCollisionDetector.v:30]
WARNING: [Synth 8-3848] Net RightStop in module/entity BGCollisionDetector does not have driver. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BGCollisionDetector.v:31]
INFO: [Synth 8-256] done synthesizing module 'BGCollisionDetector' (32#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BGCollisionDetector.v:23]
INFO: [Synth 8-638] synthesizing module 'SlugVerticalComponent' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:23]
INFO: [Synth 8-638] synthesizing module 'countUD10L' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/countUD10L.v:23]
INFO: [Synth 8-638] synthesizing module 'countUD5L' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/new/countUD5L.v:23]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized13' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized13' (32#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized14' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized14' (32#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized15' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized15' (32#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized16' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized16' (32#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized17' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized17' (32#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'mux2to1' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/new/mux2to1.v:23]
INFO: [Synth 8-256] done synthesizing module 'mux2to1' (33#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/new/mux2to1.v:23]
INFO: [Synth 8-256] done synthesizing module 'countUD5L' (34#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/new/countUD5L.v:23]
WARNING: [Synth 8-350] instance 'counter2' of module 'countUD5L' requires 9 connections, but only 7 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/countUD10L.v:36]
INFO: [Synth 8-256] done synthesizing module 'countUD10L' (35#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/countUD10L.v:23]
WARNING: [Synth 8-350] instance 'counter0' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:35]
WARNING: [Synth 8-350] instance 'counter1' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:36]
WARNING: [Synth 8-350] instance 'counter2' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:37]
WARNING: [Synth 8-350] instance 'counter3' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:38]
WARNING: [Synth 8-350] instance 'counter4' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:39]
WARNING: [Synth 8-350] instance 'counter5' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:40]
WARNING: [Synth 8-350] instance 'counter6' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:41]
WARNING: [Synth 8-350] instance 'counter7' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:42]
WARNING: [Synth 8-350] instance 'counter8' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:43]
WARNING: [Synth 8-350] instance 'counter9' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:44]
WARNING: [Synth 8-350] instance 'counterA' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:45]
WARNING: [Synth 8-350] instance 'counterB' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:46]
WARNING: [Synth 8-350] instance 'counterC' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:47]
WARNING: [Synth 8-350] instance 'counterD' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:48]
WARNING: [Synth 8-350] instance 'counterE' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:49]
WARNING: [Synth 8-350] instance 'counterF' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:50]
INFO: [Synth 8-256] done synthesizing module 'SlugVerticalComponent' (36#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:23]
INFO: [Synth 8-638] synthesizing module 'SlugHorizontalComponent' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:23]
WARNING: [Synth 8-350] instance 'counter0' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:35]
WARNING: [Synth 8-350] instance 'counter1' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:36]
WARNING: [Synth 8-350] instance 'counter2' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:37]
WARNING: [Synth 8-350] instance 'counter3' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:38]
WARNING: [Synth 8-350] instance 'counter4' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:39]
WARNING: [Synth 8-350] instance 'counter5' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:40]
WARNING: [Synth 8-350] instance 'counter6' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:41]
WARNING: [Synth 8-350] instance 'counter7' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:42]
WARNING: [Synth 8-350] instance 'counter8' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:43]
WARNING: [Synth 8-350] instance 'counter9' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:44]
WARNING: [Synth 8-350] instance 'counterA' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:45]
WARNING: [Synth 8-350] instance 'counterB' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:46]
WARNING: [Synth 8-350] instance 'counterC' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:47]
WARNING: [Synth 8-350] instance 'counterD' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:48]
WARNING: [Synth 8-350] instance 'counterE' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:49]
WARNING: [Synth 8-350] instance 'counterF' of module 'countUD10L' requires 7 connections, but only 6 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:50]
INFO: [Synth 8-256] done synthesizing module 'SlugHorizontalComponent' (37#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:23]
WARNING: [Synth 8-3848] Net SecOut in module/entity SlugGenerator does not have driver. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugGenerator.v:40]
INFO: [Synth 8-256] done synthesizing module 'SlugGenerator' (38#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugGenerator.v:23]
INFO: [Synth 8-638] synthesizing module 'VerticalObstacles' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VerticalObstacles.v:23]
INFO: [Synth 8-638] synthesizing module 'V1' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V1.v:23]
INFO: [Synth 8-256] done synthesizing module 'V1' (39#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V1.v:23]
INFO: [Synth 8-638] synthesizing module 'V2' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V2.v:23]
INFO: [Synth 8-256] done synthesizing module 'V2' (40#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V2.v:23]
INFO: [Synth 8-638] synthesizing module 'V3' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V3.v:23]
INFO: [Synth 8-256] done synthesizing module 'V3' (41#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V3.v:23]
INFO: [Synth 8-638] synthesizing module 'V4' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V4.v:23]
INFO: [Synth 8-256] done synthesizing module 'V4' (42#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V4.v:23]
INFO: [Synth 8-638] synthesizing module 'V5' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V5.v:23]
INFO: [Synth 8-256] done synthesizing module 'V5' (43#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V5.v:23]
INFO: [Synth 8-638] synthesizing module 'V6' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V6.v:23]
INFO: [Synth 8-256] done synthesizing module 'V6' (44#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V6.v:23]
INFO: [Synth 8-638] synthesizing module 'V7' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V7.v:23]
INFO: [Synth 8-256] done synthesizing module 'V7' (45#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/V7.v:23]
INFO: [Synth 8-256] done synthesizing module 'VerticalObstacles' (46#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VerticalObstacles.v:23]
INFO: [Synth 8-638] synthesizing module 'VerticalGaps' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VerticalGaps.v:23]
INFO: [Synth 8-638] synthesizing module 'VertGap1' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap1.v:23]
INFO: [Synth 8-638] synthesizing module 'GapStateMachine' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapStateMachine.v:23]
INFO: [Synth 8-638] synthesizing module 'GapStateMachineLogic' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapStateMachineLogic.v:23]
INFO: [Synth 8-256] done synthesizing module 'GapStateMachineLogic' (47#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapStateMachineLogic.v:23]
WARNING: [Synth 8-350] instance 'Q0_FF' of module 'FDRE' requires 5 connections, but only 4 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapStateMachine.v:42]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized18' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized18' (47#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
WARNING: [Synth 8-350] instance 'Q1_FF' of module 'FDRE' requires 5 connections, but only 4 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapStateMachine.v:43]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized19' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized19' (47#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
WARNING: [Synth 8-350] instance 'Q2_FF' of module 'FDRE' requires 5 connections, but only 4 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapStateMachine.v:44]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized20' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized20' (47#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
WARNING: [Synth 8-350] instance 'Q3_FF' of module 'FDRE' requires 5 connections, but only 4 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapStateMachine.v:45]
INFO: [Synth 8-256] done synthesizing module 'GapStateMachine' (48#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapStateMachine.v:23]
INFO: [Synth 8-638] synthesizing module 'GapWallDetect' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapWallDetect.v:23]
INFO: [Synth 8-256] done synthesizing module 'GapWallDetect' (49#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapWallDetect.v:23]
INFO: [Synth 8-638] synthesizing module 'SlugRedDetect' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugRedDetect.v:23]
INFO: [Synth 8-256] done synthesizing module 'SlugRedDetect' (50#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugRedDetect.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap1.v:53]
INFO: [Synth 8-638] synthesizing module 'GapHorizontalComponent' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapHorizontalComponent.v:23]
INFO: [Synth 8-256] done synthesizing module 'GapHorizontalComponent' (51#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapHorizontalComponent.v:23]
INFO: [Synth 8-638] synthesizing module 'GapVerticalComponent' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapVerticalComponent.v:23]
INFO: [Synth 8-638] synthesizing module 'GapSize' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapSize.v:23]
INFO: [Synth 8-256] done synthesizing module 'GapSize' (52#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapSize.v:23]
INFO: [Synth 8-256] done synthesizing module 'GapVerticalComponent' (53#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapVerticalComponent.v:23]
INFO: [Synth 8-256] done synthesizing module 'VertGap1' (54#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap1.v:23]
INFO: [Synth 8-638] synthesizing module 'VertGap2' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap2.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap2.v:53]
INFO: [Synth 8-256] done synthesizing module 'VertGap2' (55#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap2.v:23]
INFO: [Synth 8-638] synthesizing module 'VertGap3' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap3.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap3.v:53]
INFO: [Synth 8-256] done synthesizing module 'VertGap3' (56#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap3.v:23]
INFO: [Synth 8-638] synthesizing module 'VertGap4' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap4.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap4.v:53]
INFO: [Synth 8-256] done synthesizing module 'VertGap4' (57#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap4.v:23]
INFO: [Synth 8-638] synthesizing module 'VertGap5' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap5.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap5.v:53]
INFO: [Synth 8-256] done synthesizing module 'VertGap5' (58#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap5.v:23]
INFO: [Synth 8-638] synthesizing module 'VertGap6' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap6.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap6.v:53]
INFO: [Synth 8-256] done synthesizing module 'VertGap6' (59#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap6.v:23]
INFO: [Synth 8-638] synthesizing module 'VertGap7' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap7.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap7.v:53]
INFO: [Synth 8-256] done synthesizing module 'VertGap7' (60#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap7.v:23]
INFO: [Synth 8-256] done synthesizing module 'VerticalGaps' (61#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VerticalGaps.v:23]
WARNING: [Synth 8-350] instance 'VerticalGaps' of module 'VerticalGaps' requires 12 connections, but only 11 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopLevel.v:68]
INFO: [Synth 8-638] synthesizing module 'HorizontalObstacles' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizontalObstacles.v:23]
INFO: [Synth 8-638] synthesizing module 'H1' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H1.v:23]
INFO: [Synth 8-256] done synthesizing module 'H1' (62#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H1.v:23]
INFO: [Synth 8-638] synthesizing module 'H2' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H2.v:23]
INFO: [Synth 8-256] done synthesizing module 'H2' (63#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H2.v:23]
INFO: [Synth 8-638] synthesizing module 'H3' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H3.v:23]
INFO: [Synth 8-256] done synthesizing module 'H3' (64#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H3.v:23]
INFO: [Synth 8-638] synthesizing module 'H4' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H4.v:23]
INFO: [Synth 8-256] done synthesizing module 'H4' (65#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H4.v:23]
INFO: [Synth 8-638] synthesizing module 'H5' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H5.v:23]
INFO: [Synth 8-256] done synthesizing module 'H5' (66#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H5.v:23]
INFO: [Synth 8-638] synthesizing module 'H6' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H6.v:23]
INFO: [Synth 8-256] done synthesizing module 'H6' (67#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H6.v:23]
INFO: [Synth 8-638] synthesizing module 'H7' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H7.v:23]
INFO: [Synth 8-256] done synthesizing module 'H7' (68#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/H7.v:23]
INFO: [Synth 8-256] done synthesizing module 'HorizontalObstacles' (69#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizontalObstacles.v:23]
INFO: [Synth 8-638] synthesizing module 'HorizontalGaps' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizontalGaps.v:23]
INFO: [Synth 8-638] synthesizing module 'HorizGap1' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap1.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap1.v:53]
INFO: [Synth 8-256] done synthesizing module 'HorizGap1' (70#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap1.v:23]
INFO: [Synth 8-638] synthesizing module 'HorizGap2' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap2.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap2.v:53]
INFO: [Synth 8-256] done synthesizing module 'HorizGap2' (71#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap2.v:23]
INFO: [Synth 8-638] synthesizing module 'HorizGap3' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap3.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap3.v:53]
INFO: [Synth 8-256] done synthesizing module 'HorizGap3' (72#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap3.v:23]
INFO: [Synth 8-638] synthesizing module 'HorizGap4' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap4.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap4.v:53]
INFO: [Synth 8-256] done synthesizing module 'HorizGap4' (73#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap4.v:23]
INFO: [Synth 8-638] synthesizing module 'HorizGap5' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap5.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap5.v:53]
INFO: [Synth 8-256] done synthesizing module 'HorizGap5' (74#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap5.v:23]
INFO: [Synth 8-638] synthesizing module 'HorizGap6' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap6.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap6.v:53]
INFO: [Synth 8-256] done synthesizing module 'HorizGap6' (75#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap6.v:23]
INFO: [Synth 8-638] synthesizing module 'HorizGap7' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap7.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap7.v:53]
INFO: [Synth 8-256] done synthesizing module 'HorizGap7' (76#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap7.v:23]
INFO: [Synth 8-256] done synthesizing module 'HorizontalGaps' (77#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizontalGaps.v:23]
WARNING: [Synth 8-350] instance 'HorizontalGaps' of module 'HorizontalGaps' requires 12 connections, but only 11 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopLevel.v:72]
INFO: [Synth 8-638] synthesizing module 'qsecTicker' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/qsecTicker.v:23]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized21' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized21' (77#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized22' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized22' (77#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized23' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized23' (77#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized24' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized24' (77#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized25' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized25' (77#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-256] done synthesizing module 'qsecTicker' (78#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/qsecTicker.v:23]
INFO: [Synth 8-638] synthesizing module 'Timer' [C:/Users/bhayame/Desktop/TIMER/TIMER.srcs/sources_1/new/Timer.v:20]
INFO: [Synth 8-638] synthesizing module 'secondTicker' [C:/Users/bhayame/Desktop/TIMER/TIMER.srcs/sources_1/new/secondTicker.v:23]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized26' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized26' (78#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized27' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized27' (78#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized28' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized28' (78#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized29' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized29' (78#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized30' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized30' (78#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized31' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized31' (78#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-256] done synthesizing module 'secondTicker' (79#1) [C:/Users/bhayame/Desktop/TIMER/TIMER.srcs/sources_1/new/secondTicker.v:23]
INFO: [Synth 8-638] synthesizing module 'countU4' [C:/Users/bhayame/Desktop/TIMER/TIMER.srcs/sources_1/new/countU4.v:23]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized32' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized32' (79#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized33' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized33' (79#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized34' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized34' (79#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized35' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized35' (79#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-256] done synthesizing module 'countU4' (80#1) [C:/Users/bhayame/Desktop/TIMER/TIMER.srcs/sources_1/new/countU4.v:23]
INFO: [Synth 8-638] synthesizing module 'countU3' [C:/Users/bhayame/Desktop/TIMER/TIMER.srcs/sources_1/new/countU3.v:23]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized36' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized36' (80#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized37' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized37' (80#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized38' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized38' (80#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-256] done synthesizing module 'countU3' (81#1) [C:/Users/bhayame/Desktop/TIMER/TIMER.srcs/sources_1/new/countU3.v:23]
INFO: [Synth 8-256] done synthesizing module 'Timer' (82#1) [C:/Users/bhayame/Desktop/TIMER/TIMER.srcs/sources_1/new/Timer.v:20]
INFO: [Synth 8-638] synthesizing module 'RingCounter' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Desktop/Lab 4/Lab 4.srcs/sources_1/new/RingCounter.v:23]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized39' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized39' (82#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized40' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized40' (82#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
INFO: [Synth 8-638] synthesizing module 'FDRE__parameterized41' [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FDRE__parameterized41' (82#1) [C:/Xilinx/Vivado/2016.3/scripts/rt/data/unisim_comp.v:3964]
WARNING: [Synth 8-3848] Net reset in module/entity RingCounter does not have driver. [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Desktop/Lab 4/Lab 4.srcs/sources_1/new/RingCounter.v:29]
INFO: [Synth 8-256] done synthesizing module 'RingCounter' (83#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Desktop/Lab 4/Lab 4.srcs/sources_1/new/RingCounter.v:23]
INFO: [Synth 8-638] synthesizing module 'Selector' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Desktop/Lab 4/Lab 4.srcs/sources_1/new/Selector.v:23]
INFO: [Synth 8-256] done synthesizing module 'Selector' (84#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Desktop/Lab 4/Lab 4.srcs/sources_1/new/Selector.v:23]
INFO: [Synth 8-638] synthesizing module 'hex7seg' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Desktop/Lab 4/Lab 4.srcs/sources_1/new/hex7seg.v:23]
INFO: [Synth 8-638] synthesizing module 'm8_1e' [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/new/m8_1e.v:23]
INFO: [Synth 8-256] done synthesizing module 'm8_1e' (85#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/new/m8_1e.v:23]
INFO: [Synth 8-256] done synthesizing module 'hex7seg' (86#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Desktop/Lab 4/Lab 4.srcs/sources_1/new/hex7seg.v:23]
WARNING: [Synth 8-350] instance 'secGenerator' of module 'countU10' requires 4 connections, but only 3 given [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopLevel.v:85]
INFO: [Synth 8-256] done synthesizing module 'TopLevel' (87#1) [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopLevel.v:23]
WARNING: [Synth 8-3917] design TopLevel has port led[15] driven by constant 0
WARNING: [Synth 8-3917] design TopLevel has port led[14] driven by constant 0
WARNING: [Synth 8-3917] design TopLevel has port led[13] driven by constant 0
WARNING: [Synth 8-3917] design TopLevel has port led[12] driven by constant 0
WARNING: [Synth 8-3917] design TopLevel has port led[11] driven by constant 0
WARNING: [Synth 8-3917] design TopLevel has port led[10] driven by constant 0
WARNING: [Synth 8-3917] design TopLevel has port led[9] driven by constant 0
WARNING: [Synth 8-3917] design TopLevel has port led[4] driven by constant 0
WARNING: [Synth 8-3331] design HorizGap7 has unconnected port reset
WARNING: [Synth 8-3331] design HorizGap6 has unconnected port reset
WARNING: [Synth 8-3331] design HorizGap5 has unconnected port reset
WARNING: [Synth 8-3331] design HorizGap4 has unconnected port reset
WARNING: [Synth 8-3331] design HorizGap3 has unconnected port reset
WARNING: [Synth 8-3331] design HorizGap2 has unconnected port reset
WARNING: [Synth 8-3331] design HorizGap1 has unconnected port reset
WARNING: [Synth 8-3331] design H7 has unconnected port Hcount[2]
WARNING: [Synth 8-3331] design H7 has unconnected port Hcount[1]
WARNING: [Synth 8-3331] design H7 has unconnected port Hcount[0]
WARNING: [Synth 8-3331] design H6 has unconnected port Hcount[2]
WARNING: [Synth 8-3331] design H6 has unconnected port Hcount[1]
WARNING: [Synth 8-3331] design H6 has unconnected port Hcount[0]
WARNING: [Synth 8-3331] design H5 has unconnected port Hcount[2]
WARNING: [Synth 8-3331] design H5 has unconnected port Hcount[1]
WARNING: [Synth 8-3331] design H5 has unconnected port Hcount[0]
WARNING: [Synth 8-3331] design H4 has unconnected port Hcount[2]
WARNING: [Synth 8-3331] design H4 has unconnected port Hcount[1]
WARNING: [Synth 8-3331] design H4 has unconnected port Hcount[0]
WARNING: [Synth 8-3331] design H3 has unconnected port Hcount[2]
WARNING: [Synth 8-3331] design H3 has unconnected port Hcount[1]
WARNING: [Synth 8-3331] design H3 has unconnected port Hcount[0]
WARNING: [Synth 8-3331] design H2 has unconnected port Hcount[2]
WARNING: [Synth 8-3331] design H2 has unconnected port Hcount[1]
WARNING: [Synth 8-3331] design H2 has unconnected port Hcount[0]
WARNING: [Synth 8-3331] design H1 has unconnected port Hcount[2]
WARNING: [Synth 8-3331] design H1 has unconnected port Hcount[1]
WARNING: [Synth 8-3331] design H1 has unconnected port Hcount[0]
WARNING: [Synth 8-3331] design VertGap7 has unconnected port reset
WARNING: [Synth 8-3331] design VertGap6 has unconnected port reset
WARNING: [Synth 8-3331] design VertGap5 has unconnected port reset
WARNING: [Synth 8-3331] design VertGap4 has unconnected port reset
WARNING: [Synth 8-3331] design VertGap3 has unconnected port reset
WARNING: [Synth 8-3331] design VertGap2 has unconnected port reset
WARNING: [Synth 8-3331] design VertGap1 has unconnected port reset
WARNING: [Synth 8-3331] design V7 has unconnected port Vcount[2]
WARNING: [Synth 8-3331] design V7 has unconnected port Vcount[1]
WARNING: [Synth 8-3331] design V7 has unconnected port Vcount[0]
WARNING: [Synth 8-3331] design V6 has unconnected port Vcount[2]
WARNING: [Synth 8-3331] design V6 has unconnected port Vcount[1]
WARNING: [Synth 8-3331] design V6 has unconnected port Vcount[0]
WARNING: [Synth 8-3331] design V5 has unconnected port Vcount[2]
WARNING: [Synth 8-3331] design V5 has unconnected port Vcount[1]
WARNING: [Synth 8-3331] design V5 has unconnected port Vcount[0]
WARNING: [Synth 8-3331] design V4 has unconnected port Vcount[2]
WARNING: [Synth 8-3331] design V4 has unconnected port Vcount[1]
WARNING: [Synth 8-3331] design V4 has unconnected port Vcount[0]
WARNING: [Synth 8-3331] design V3 has unconnected port Vcount[2]
WARNING: [Synth 8-3331] design V3 has unconnected port Vcount[1]
WARNING: [Synth 8-3331] design V3 has unconnected port Vcount[0]
WARNING: [Synth 8-3331] design V2 has unconnected port Vcount[2]
WARNING: [Synth 8-3331] design V2 has unconnected port Vcount[1]
WARNING: [Synth 8-3331] design V2 has unconnected port Vcount[0]
WARNING: [Synth 8-3331] design V1 has unconnected port Vcount[2]
WARNING: [Synth 8-3331] design V1 has unconnected port Vcount[1]
WARNING: [Synth 8-3331] design V1 has unconnected port Vcount[0]
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port DwStop
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port LeftStop
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port RightStop
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port Hcount[9]
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port Hcount[8]
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port Hcount[7]
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port Hcount[6]
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port Hcount[5]
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port Hcount[4]
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port Hcount[3]
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port Hcount[2]
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port Hcount[1]
WARNING: [Synth 8-3331] design BGCollisionDetector has unconnected port Hcount[0]
WARNING: [Synth 8-3331] design SlugPositionSet has unconnected port Hcount[0]
WARNING: [Synth 8-3331] design BorderGenerator has unconnected port Hcount[2]
WARNING: [Synth 8-3331] design BorderGenerator has unconnected port Hcount[1]
WARNING: [Synth 8-3331] design BorderGenerator has unconnected port Hcount[0]
WARNING: [Synth 8-3331] design BorderGenerator has unconnected port Vcount[2]
WARNING: [Synth 8-3331] design BorderGenerator has unconnected port Vcount[1]
WARNING: [Synth 8-3331] design BorderGenerator has unconnected port Vcount[0]
WARNING: [Synth 8-3331] design clkcntrl4 has unconnected port qsec
WARNING: [Synth 8-3331] design TopStateMachineLogic has unconnected port clk
WARNING: [Synth 8-3331] design TopLevel has unconnected port sw[15]
WARNING: [Synth 8-3331] design TopLevel has unconnected port sw[14]
WARNING: [Synth 8-3331] design TopLevel has unconnected port sw[13]
WARNING: [Synth 8-3331] design TopLevel has unconnected port sw[12]
WARNING: [Synth 8-3331] design TopLevel has unconnected port sw[11]
WARNING: [Synth 8-3331] design TopLevel has unconnected port sw[10]
WARNING: [Synth 8-3331] design TopLevel has unconnected port sw[9]
WARNING: [Synth 8-3331] design TopLevel has unconnected port sw[8]
WARNING: [Synth 8-3331] design TopLevel has unconnected port sw[7]
WARNING: [Synth 8-3331] design TopLevel has unconnected port sw[3]
WARNING: [Synth 8-3331] design TopLevel has unconnected port sw[2]
WARNING: [Synth 8-3331] design TopLevel has unconnected port sw[1]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:04:08 ; elapsed = 00:33:22 . Memory (MB): peak = 1338.102 ; gain = 1125.145
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
WARNING: [Synth 8-3295] tying undriven pin Q0_FF:R to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachine.v:45]
WARNING: [Synth 8-3295] tying undriven pin Q1_FF:R to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachine.v:46]
WARNING: [Synth 8-3295] tying undriven pin Q2_FF:R to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachine.v:47]
WARNING: [Synth 8-3295] tying undriven pin Q3_FF:R to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopStateMachine.v:48]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BorderGenerator.v:36]
WARNING: [Synth 8-3295] tying undriven pin FlashModule:sec to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/BorderGenerator.v:37]
WARNING: [Synth 8-3295] tying undriven pin counter0:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:35]
WARNING: [Synth 8-3295] tying undriven pin counter1:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:36]
WARNING: [Synth 8-3295] tying undriven pin counter2:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:37]
WARNING: [Synth 8-3295] tying undriven pin counter3:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:38]
WARNING: [Synth 8-3295] tying undriven pin counter4:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:39]
WARNING: [Synth 8-3295] tying undriven pin counter5:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:40]
WARNING: [Synth 8-3295] tying undriven pin counter6:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:41]
WARNING: [Synth 8-3295] tying undriven pin counter7:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:42]
WARNING: [Synth 8-3295] tying undriven pin counter8:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:43]
WARNING: [Synth 8-3295] tying undriven pin counter9:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:44]
WARNING: [Synth 8-3295] tying undriven pin counterA:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:45]
WARNING: [Synth 8-3295] tying undriven pin counterB:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:46]
WARNING: [Synth 8-3295] tying undriven pin counterC:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:47]
WARNING: [Synth 8-3295] tying undriven pin counterD:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:48]
WARNING: [Synth 8-3295] tying undriven pin counterE:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:49]
WARNING: [Synth 8-3295] tying undriven pin counterF:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugVerticalComponent.v:50]
WARNING: [Synth 8-3295] tying undriven pin counter0:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:35]
WARNING: [Synth 8-3295] tying undriven pin counter1:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:36]
WARNING: [Synth 8-3295] tying undriven pin counter2:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:37]
WARNING: [Synth 8-3295] tying undriven pin counter3:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:38]
WARNING: [Synth 8-3295] tying undriven pin counter4:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:39]
WARNING: [Synth 8-3295] tying undriven pin counter5:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:40]
WARNING: [Synth 8-3295] tying undriven pin counter6:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:41]
WARNING: [Synth 8-3295] tying undriven pin counter7:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:42]
WARNING: [Synth 8-3295] tying undriven pin counter8:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:43]
WARNING: [Synth 8-3295] tying undriven pin counter9:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:44]
WARNING: [Synth 8-3295] tying undriven pin counterA:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:45]
WARNING: [Synth 8-3295] tying undriven pin counterB:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:46]
WARNING: [Synth 8-3295] tying undriven pin counterC:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:47]
WARNING: [Synth 8-3295] tying undriven pin counterD:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:48]
WARNING: [Synth 8-3295] tying undriven pin counterE:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:49]
WARNING: [Synth 8-3295] tying undriven pin counterF:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugHorizontalComponent.v:50]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugGenerator.v:43]
WARNING: [Synth 8-3295] tying undriven pin FlashModule:sec to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/SlugGenerator.v:44]
WARNING: [Synth 8-3295] tying undriven pin Q0_FF:R to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapStateMachine.v:42]
WARNING: [Synth 8-3295] tying undriven pin Q1_FF:R to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapStateMachine.v:43]
WARNING: [Synth 8-3295] tying undriven pin Q2_FF:R to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapStateMachine.v:44]
WARNING: [Synth 8-3295] tying undriven pin Q3_FF:R to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/GapStateMachine.v:45]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap1.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap2.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap3.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap4.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap5.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap6.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/VertGap7.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap1.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap2.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap3.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap4.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap5.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap6.v:53]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/HorizGap7.v:53]
WARNING: [Synth 8-3295] tying undriven pin ff0:R to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Desktop/Lab 4/Lab 4.srcs/sources_1/new/RingCounter.v:29]
WARNING: [Synth 8-3295] tying undriven pin ff1:R to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Desktop/Lab 4/Lab 4.srcs/sources_1/new/RingCounter.v:30]
WARNING: [Synth 8-3295] tying undriven pin ff2:R to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Desktop/Lab 4/Lab 4.srcs/sources_1/new/RingCounter.v:31]
WARNING: [Synth 8-3295] tying undriven pin ff3:R to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/imports/Desktop/Lab 4/Lab 4.srcs/sources_1/new/RingCounter.v:32]
WARNING: [Synth 8-3295] tying undriven pin BorderGenerator:clk to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopLevel.v:62]
WARNING: [Synth 8-3295] tying undriven pin VerticalGaps:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopLevel.v:68]
WARNING: [Synth 8-3295] tying undriven pin HorizontalGaps:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopLevel.v:72]
WARNING: [Synth 8-3295] tying undriven pin secGenerator:reset to constant 0 [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/sources_1/new/TopLevel.v:85]
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:04:09 ; elapsed = 00:33:22 . Memory (MB): peak = 1338.102 ; gain = 1125.145
---------------------------------------------------------------------------------
INFO: [Netlist 29-17] Analyzing 52 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-140] Inserted 1 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 14 OBUFs to IO ports without IO buffers.
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/constrs_1/imports/Desktop/Basys3_Master.xdc]
Finished Parsing XDC File [C:/Users/bhayame/Desktop/Lab 7/Lab 7.srcs/constrs_1/imports/Desktop/Basys3_Master.xdc]
Completed Processing XDC Constraints
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
refresh_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 1395.656 ; gain = 98.883
launch_runs impl_1 -to_step write_bitstream
[Sat Dec 01 20:55:12 2018] Launched impl_1...
Run output will be captured here: C:/Users/bhayame/Desktop/Lab 7/Lab 7.runs/impl_1/runme.log
set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
set_property PROGRAM.FILE {C:/Users/bhayame/Desktop/Lab 7/Lab 7.runs/impl_1/TopLevel.bit} [lindex [get_hw_devices xc7a35t_0] 0]
program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream
[Sat Dec 01 20:59:55 2018] Launched synth_1...
Run output will be captured here: C:/Users/bhayame/Desktop/Lab 7/Lab 7.runs/synth_1/runme.log
[Sat Dec 01 20:59:55 2018] Launched impl_1...
Run output will be captured here: C:/Users/bhayame/Desktop/Lab 7/Lab 7.runs/impl_1/runme.log
set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
set_property PROGRAM.FILE {C:/Users/bhayame/Desktop/Lab 7/Lab 7.runs/impl_1/TopLevel.bit} [lindex [get_hw_devices xc7a35t_0] 0]
program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
archive_project {C:/Users/bhayame/Desktop/Lab 7 DONE.xpr.zip} -temp_dir {C:/Users/bhayame/Desktop/Lab 7/.Xil/Vivado-5944-BE104PC19} -force
INFO: [Coretcl 2-137] starting archive...
INFO: [Coretcl 2-1499] Saving project copy to temporary location 'C:/Users/bhayame/Desktop/Lab 7/.Xil/Vivado-5944-BE104PC19' for archiving project
Scanning sources...
Finished scanning sources
WARNING: [filemgmt 56-3] IP Output Repository Path: Could not find the directory 'C:/Users/bhayame/Desktop/Lab 7/Lab 7.cache/ip'.
INFO: [Coretcl 2-1211] Creating project copy for archival...
INFO: [Coretcl 2-1213] Including run results for 'synth_1'
INFO: [Coretcl 2-1213] Including run results for 'impl_1'
INFO: [Coretcl 2-1212] Importing remotely added design sources and verilog include files (if any)...
INFO: [filemgmt 20-334] All file(s) are already imported in fileset: 'constrs_1'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'constrs_1'
INFO: [filemgmt 20-334] All file(s) are already imported in fileset: 'sim_1'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sim_1'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sources_1'
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