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42 lines
1.3 KiB
Verilog
42 lines
1.3 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 11/30/2018 06:09:53 PM
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// Design Name:
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// Module Name: secondTicker
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module secondTicker(
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input clk,
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input frame,
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input reset,
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output sec
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);
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wire [5:0] Q;
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FDRE #(.INIT(1'b0) ) ff0 (.C(clk), .R(reset), .CE(frame), .D(~Q[0]), .Q(Q[0]));
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FDRE #(.INIT(1'b0) ) ff1 (.C(clk), .R(reset), .CE(frame & Q[0]), .D(~Q[1]), .Q(Q[1]));
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FDRE #(.INIT(1'b0) ) ff2 (.C(clk), .R(reset), .CE(frame & Q[0] & Q[1]), .D(~Q[2]), .Q(Q[2]));
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FDRE #(.INIT(1'b0) ) ff3 (.C(clk), .R(reset), .CE(frame & Q[0] & Q[1] & Q[2]), .D(~Q[3]), .Q(Q[3]));
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FDRE #(.INIT(1'b0) ) ff4 (.C(clk), .R(reset), .CE(frame & Q[0] & Q[1] & Q[2] & Q[3]), .D(~Q[4]), .Q(Q[4]));
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FDRE #(.INIT(1'b0) ) ff5 (.C(clk), .R(reset), .CE(frame & Q[0] & Q[1] & Q[2] & Q[3] & Q[4]), .D(~Q[5]), .Q(Q[5]));
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assign sec = Q[5] & Q[4] & Q[3] & Q[2] & Q[1] & Q[0];
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endmodule
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