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41 lines
1.3 KiB
Verilog
41 lines
1.3 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 11/30/2018 07:02:00 PM
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// Design Name:
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// Module Name: Timer
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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// // Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module Timer(
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input clk,
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input frame,
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input CE,
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input reset,
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output [15:0] Q
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);
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wire sec, secEdge;
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wire UTC1, UTC2, UTC3, UTC4;
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secondTicker secondTicker (.clk(clk),.frame(frame),.reset(reset), .sec(sec));
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EdgeDetector EdgeDetector (.btn(sec), .clkin(clk), .out(secEdge));
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countU4 seconds (.clk(clk), .CE(CE & secEdge), .reset(reset | (UTC1 & secEdge)), .UTC(UTC1), .Q(Q[3:0]));
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countU3 tenSeconds (.clk(clk), .CE(CE & secEdge & UTC1), .reset(reset | (UTC1 & UTC2 & secEdge)), .UTC(UTC2), .Q(Q[7:4]));
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countU4 minutes (.clk(clk), .CE(CE & secEdge & UTC1 & UTC2), .reset(reset | (UTC1 & UTC2 & UTC3 & secEdge)), .UTC(UTC3), .Q(Q[11:8]));
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countU3 tenMinutes (.clk(clk), .CE(CE & secEdge & UTC1 & UTC2 & UTC3), .reset(reset | (UTC1 & UTC2 & UTC3 & UTC4 & secEdge)), .Q(Q[15:12]), .UTC(UTC4));
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endmodule
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