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36 lines
948 B
Verilog
36 lines
948 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 10/31/2018 05:56:37 PM
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// Design Name:
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// Module Name: RingCounter
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module RingCounter(
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input advance,
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input clkin,
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input reset,
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output [3:0] Q
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);
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FDRE #(.INIT(1'b1) ) ff0 (.C(clkin), .R(reset), .CE(advance), .D(Q[3]), .Q(Q[0]));
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FDRE #(.INIT(1'b0) ) ff1 (.C(clkin), .R(reset), .CE(advance), .D(Q[0]), .Q(Q[1]));
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FDRE #(.INIT(1'b0) ) ff2 (.C(clkin), .R(reset), .CE(advance), .D(Q[1]), .Q(Q[2]));
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FDRE #(.INIT(1'b0) ) ff3 (.C(clkin), .R(reset), .CE(advance), .D(Q[2]), .Q(Q[3]));
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endmodule
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