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38 lines
716 B
Verilog
38 lines
716 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 10/31/2018 06:17:39 PM
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// Design Name:
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// Module Name: EdgeDetector
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module EdgeDetector(
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input btn,
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input clkin,
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output out
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);
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wire t0;
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FDRE #(.INIT(1'b0) ) ff (.C(clkin), .R(1'b0), .CE(1), .D(btn), .Q(t0));
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assign out = ~t0 & btn;
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endmodule
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