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41 lines
1.1 KiB
Verilog
41 lines
1.1 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 10/30/2018 10:37:10 PM
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// Design Name:
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// Module Name: countUD5L
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module countU5(
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input clk,
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input Up,
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input reset,
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output [4:0] Q,
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output UTC
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);
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wire d0, d1, d2, d3, d4;
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FDRE #(.INIT(1'b0) ) ff0 (.C(clk), .R(reset), .CE(Up), .D(~Q[0]), .Q(Q[0]));
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FDRE #(.INIT(1'b0) ) ff1 (.C(clk), .R(reset), .CE(Up & Q[0]), .D(~Q[1]), .Q(Q[1]));
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FDRE #(.INIT(1'b0) ) ff2 (.C(clk), .R(reset), .CE(Up & Q[0] & Q[1]), .D(~Q[2]), .Q(Q[2]));
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FDRE #(.INIT(1'b0) ) ff3 (.C(clk), .R(reset), .CE(Up & Q[0] & Q[1] & Q[2]), .D(~Q[3]), .Q(Q[3]));
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FDRE #(.INIT(1'b0) ) ff4 (.C(clk), .R(reset), .CE(Up & Q[0] & Q[1] & Q[2] & Q[3]), .D(~Q[4]), .Q(Q[4]));
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assign UTC = Q[0] & Q[1] & Q[2] & Q[3] & Q[4];
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endmodule
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