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39 lines
764 B
Verilog
39 lines
764 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 11/27/2018 04:39:07 PM
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// Design Name:
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// Module Name: btnChecker
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module btnChecker(
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input Uin,
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input Din,
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input Lin,
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input Rin,
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output Uout,
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output Dout,
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output Lout,
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output Rout
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);
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assign Uout = Uin & ~Din;
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assign Dout = ~Uin & Din;
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assign Lout = Lin & ~Rin;
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assign Rout = ~Lin & Rin;
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endmodule
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