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34 lines
824 B
Verilog
34 lines
824 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 12/01/2018 06:45:09 PM
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// Design Name:
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// Module Name: WinDetector
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module WinDetector(
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input [9:0] Hcount,
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input [9:0] Vcount,
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input [3:0] Green,
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output WinDetect
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);
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assign WinDetect = (Hcount >= 10'b1001110010) & (Hcount <= 10'b1001110111) & (Vcount >= 10'b0111010010) &
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(Vcount <= 10'b0111010111) & (Green[3] & Green[2] & Green[1] & Green[0]);
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endmodule
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