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45 lines
1.5 KiB
Verilog
45 lines
1.5 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 11/27/2018 09:06:32 PM
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// Design Name:
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// Module Name: VerticalObstacles
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module VerticalObstacles(
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input [9:0] Hcount,
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input [9:0] Vcount,
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output[3:0] Red
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);
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wire [3:0] Red1, Red2, Red3, Red4, Red5, Red6, Red7;
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V1 V1 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red1[3:0]}));
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V2 V2 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red2[3:0]}));
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V3 V3 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red3[3:0]}));
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V4 V4 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red4[3:0]}));
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V5 V5 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red5[3:0]}));
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V6 V6 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red6[3:0]}));
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V7 V7 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red7[3:0]}));
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assign Red[3] = Red3[3] | Red1[3] | Red2[3] | Red4[3]| Red5[3] | Red6[3:0] | Red7[3:0];
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assign Red[2] = Red3[2] | Red1[2] | Red2[2] | Red4[2]| Red5[2] | Red6[3:0] | Red7[3:0];
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assign Red[1] = Red3[1] | Red1[1] | Red2[1] | Red4[1]| Red5[1] | Red6[3:0] | Red7[3:0];
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assign Red[0] = Red3[0] | Red1[0] | Red2[0] | Red4[0]| Red5[0] | Red6[3:0] | Red7[3:0];
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endmodule
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