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44 lines
1.2 KiB
Verilog
44 lines
1.2 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 11/22/2018 02:38:22 PM
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// Design Name:
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// Module Name: HorizontalCounter
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module VerticalCounter(
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input clk,
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input enable,
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output zeroDetect,
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output endDetect,
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output InActiveZone,
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output OutActiveZone,
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output reset,
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output [9:0] Q
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);
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countU10 counter (.clk(clk), .Up(enable), .reset(reset), .Q(Q));
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assign zeroDetect = ~Q[9] & Q[8] & Q[7] & Q[6] & Q[5] & ~Q[4] & Q[3] & ~Q[2] & ~Q[1] & Q[0];
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assign endDetect = ~Q[9] & Q[8] & Q[7] & Q[6] & Q[5] & ~Q[4] & Q[3] & ~Q[2] & Q[1] & Q[0];
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assign InActiveZone = ~Q[9] & ~Q[8] & ~Q[7] & ~Q[6] & ~Q[5] & ~Q[4] & ~Q[3] & ~Q[2] & ~Q[1] & ~Q[0];
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assign OutActiveZone = ~Q[9] & Q[8] & Q[7] & Q[6] & Q[5] & ~Q[4] & ~Q[3] & ~Q[2] & ~Q[1] & ~Q[0];
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assign reset = Q[9] & ~Q[8] & ~Q[7] & ~Q[6] & ~Q[5] & ~Q[4] & Q[3] & Q[2] & ~Q[1] & Q[0];
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endmodule
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