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75 lines
2.6 KiB
Verilog
75 lines
2.6 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 11/22/2018 03:45:41 PM
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// Design Name:
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// Module Name: Hsync
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module VGAController(
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input clk,
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input [3:0] RedIn,
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input [3:0] BlueIn,
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input [3:0] GreenIn,
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output Hsync,
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output Vsync,
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output frame,
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output [3:0] vgaRed,
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output [3:0] vgaBlue,
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output [3:0] vgaGreen,
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output VBlank,
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output HBlank,
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output [9:0] Hcount,
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output [9:0] Vcount
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);
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wire HzeroDetect, HendDetect, VzeroDetect, VendDetect, HInActiveZone, HOutActiveZone, VInActiveZone, VOutActiveZone, Q0, Q1, Q2, Q3;
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HorizontalCounter HorizontalCounter (.clk(clk), .reset(), .enable(1'b1), .zeroDetect(HzeroDetect), .endDetect(HendDetect),
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.InActiveZone(HInActiveZone), .OutActiveZone(HOutActiveZone), .Q(Hcount));
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FDRE #(.INIT(1'b0) ) HsyncGen (.C(clk), .R(HendDetect), .CE(HzeroDetect | HendDetect), .D(HzeroDetect), .Q(Q0));
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FDRE #(.INIT(1'b0) ) HActiveZone (.C(clk), .R(HOutActiveZone), .CE(HInActiveZone | HOutActiveZone), .D(HInActiveZone), .Q(Q2));
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VerticalCounter VerticalCounter (.clk(clk), .reset(), .enable(HzeroDetect), .zeroDetect(VzeroDetect), .endDetect(VendDetect),
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.InActiveZone(VInActiveZone), .OutActiveZone(VOutActiveZone), .Q(Vcount));
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FDRE #(.INIT(1'b0) ) VsyncGen (.C(clk), .R(VendDetect), .CE(VzeroDetect | VendDetect), .D(VzeroDetect), .Q(Q1));
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FDRE #(.INIT(1'b0) ) VActiveZone (.C(clk), .R(VOutActiveZone), .CE(VInActiveZone | VOutActiveZone), .D(VInActiveZone), .Q(Q3));
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EdgeDetector EdgeDetector (.btn(~Q1), .clkin(clk), .out(frame));
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assign VBlank = ~Q3;
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assign HBlank = ~Q2;
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assign vgaRed[3] = RedIn[3] & Q2 & Q3;
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assign vgaRed[2] = RedIn[2] & Q2 & Q3;
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assign vgaRed[1] = RedIn[1] & Q2 & Q3;
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assign vgaRed[0] = RedIn[0] & Q2 & Q3;
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assign vgaBlue[3] = BlueIn[3] & Q2 & Q3;
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assign vgaBlue[2] = BlueIn[2] & Q2 & Q3;
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assign vgaBlue[1] = BlueIn[1] & Q2 & Q3;
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assign vgaBlue[0] = BlueIn[0] & Q2 & Q3;
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assign vgaGreen[3] = GreenIn[3] & Q2 & Q3;
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assign vgaGreen[2] = GreenIn[2] & Q2 & Q3;
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assign vgaGreen[1] = GreenIn[1] & Q2 & Q3;
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assign vgaGreen[0] = GreenIn[0] & Q2 & Q3;
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assign Hsync = ~Q0;
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assign Vsync = ~Q1;
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endmodule
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