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43 lines
2.0 KiB
Verilog
43 lines
2.0 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 11/27/2018 05:22:28 PM
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// Design Name:
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// Module Name: VertObstacle
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module V2(
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input [9:0] Hcount,
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input [9:0] Vcount,
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output[3:0] Red
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);
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assign Red[3] = ((~Hcount[9] & ~Hcount[8] & Hcount[7] & Hcount[6] & ~Hcount[5] & Hcount[4] & ~Hcount [3] & ~Hcount[2] & ~Hcount[1] & ~Hcount[0]) |
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(~Hcount[9] & ~Hcount[8] & Hcount[7] & Hcount[6] & ~Hcount[5] & Hcount[4] & ~Hcount [3] & ~Hcount[2] & ~Hcount[1] & Hcount[0]) |
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(~Hcount[9] & ~Hcount[8] & Hcount[7] & Hcount[6] & ~Hcount[5] & Hcount[4] & ~Hcount [3] & ~Hcount[2] & Hcount[1] & ~Hcount[0]) |
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(~Hcount[9] & ~Hcount[8] & Hcount[7] & Hcount[6] & ~Hcount[5] & Hcount[4] & ~Hcount [3] & ~Hcount[2] & Hcount[1] & Hcount[0]) |
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(~Hcount[9] & ~Hcount[8] & Hcount[7] & Hcount[6] & ~Hcount[5] & Hcount[4] & ~Hcount [3] & Hcount[2] & ~Hcount[1] & ~Hcount[0]) |
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(~Hcount[9] & ~Hcount[8] & Hcount[7] & Hcount[6] & ~Hcount[5] & Hcount[4] & ~Hcount [3] & Hcount[2] & ~Hcount[1] & Hcount[0]) |
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(~Hcount[9] & ~Hcount[8] & Hcount[7] & Hcount[6] & ~Hcount[5] & Hcount[4] & ~Hcount [3] & Hcount[2] & Hcount[1] & ~Hcount[0]) |
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(~Hcount[9] & ~Hcount[8] & Hcount[7] & Hcount[6] & ~Hcount[5] & Hcount[4] & ~Hcount [3] & Hcount[2] & Hcount[1] & Hcount[0])) &
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((Vcount[9] | Vcount[8] | Vcount[7] | Vcount[6] | Vcount[5] | Vcount[4] | Vcount[3]) &
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(~(~Vcount[9] & Vcount[8] & Vcount[7] & Vcount[6] & ~Vcount[5] & Vcount[4] & Vcount[3])));
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assign Red[2] = Red[3];
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assign Red[1] = Red[3];
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assign Red[0] = Red[3];
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endmodule
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