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https://github.com/MiSTer-devel/SlugCross_MiSTer.git
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62 lines
2.3 KiB
Verilog
62 lines
2.3 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 11/26/2018 06:03:50 PM
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// Design Name:
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// Module Name: SlugGenerator
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module SlugGenerator(
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input btnU,
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input btnD,
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input btnL,
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input btnR,
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input reset,
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input frame,
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input sec,
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input clk,
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input flash,
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input [9:0] Hcount,
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input [9:0] Vcount,
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output [3:0] Green
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);
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wire GreenVert, GreenHoriz, btnUchecked, btnDchecked, btnRchecked, btnLchecked, load, flashOut, secEdge;
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wire UpStop, DwStop, LeftStop, RightStop;
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wire [9:0] SecOut;
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EdgeDetector SecEdge (.btn(sec), .clkin(clk), .out(secEdge));
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countU10 secGenerator(.clk(clk), .Up(secEdge), .Q(SecOut));
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FlashModule FlashModule (.flash(flash), .sec(SecOut[0]), .flashOut(flashOut));
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SlugPositionSet SlugPositionSet (.Hcount(Hcount[9:0]), .GreenHoriz(GreenHoriz), .load(load));
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btnChecker btnChecker (.Uin(btnU), .Din(btnD), .Rin(btnR), .Lin(btnL), .Uout(btnUchecked), .Dout(btnDchecked), .Rout(btnRchecked), .Lout(btnLchecked));
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BGCollisionDetector BGCollisionDetector(.Hcount(Hcount), .Vcount(Vcount), .btnU(btnUchecked), .Green(GreenHoriz & GreenVert), .UpStop(UpStop), .DwStop(DwStop),
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.LeftStop(LeftStop), .RightStop(RightStop));
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SlugVerticalComponent SlugVerticalComponent(.Vcount(Vcount[9:0]), .frame(frame), .clk(clk), .btnU(UpStop),
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.btnD(btnDchecked & ~DwStop), .reset(load | reset), .Green(GreenVert));
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SlugHorizontalComponent SlugHorizontalComponent(.Hcount(Hcount[9:0]), .frame(frame), .clk(clk), .btnR(btnRchecked & ~RightStop),
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.btnL(btnLchecked & ~LeftStop), .reset(load | reset), .Green(GreenHoriz));
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assign Green[3] = (GreenVert & GreenHoriz) & ~flashOut;
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assign Green[2] = (GreenVert & GreenHoriz) & ~flashOut;
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assign Green[1] = (GreenVert & GreenHoriz) & ~flashOut;
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assign Green[0] = (GreenVert & GreenHoriz) & ~flashOut;
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endmodule
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