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36 lines
989 B
Verilog
36 lines
989 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 11/27/2018 05:22:28 PM
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// Design Name:
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// Module Name: VertObstacle
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module H2(
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input [9:0] Hcount,
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input [9:0] Vcount,
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output[3:0] Red
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);
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assign Red[3] = (Vcount >= 10'b0010000000) & (Vcount <= 10'b0010000111) &
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((Hcount[9] | Hcount[8] | Hcount[7] | Hcount[6] | Hcount[5] | Hcount[4] | Hcount[3]) &
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(~(Hcount[9] & ~Hcount[8] & ~Hcount[7] & Hcount[6] & Hcount[5] & Hcount[4] & Hcount[3])));
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assign Red[2] = Red[3];
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assign Red[1] = Red[3];
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assign Red[0] = Red[3];
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endmodule
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