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38 lines
1.1 KiB
Verilog
38 lines
1.1 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 11/28/2018 02:02:09 PM
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// Design Name:
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// Module Name: GapHorizontalComponent
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module GapHorizontalComponent(
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input [9:0] Hcount,
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input [3:0] RedIn,
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input [9:0] LeftStartingPosition,
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input [9:0] RightStartingPosition,
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output[3:0] RedOut
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);
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assign RedOut[3] = ((~((LeftStartingPosition <= Hcount) & (Hcount <= RightStartingPosition))) & RedIn[3]);
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assign RedOut[2] = ((~((LeftStartingPosition <= Hcount) & (Hcount <= RightStartingPosition))) & RedIn[2]);
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assign RedOut[1] = ((~((LeftStartingPosition <= Hcount) & (Hcount <= RightStartingPosition))) & RedIn[1]);
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assign RedOut[0] = ((~((LeftStartingPosition <= Hcount) & (Hcount <= RightStartingPosition))) & RedIn[0]);
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endmodule
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