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https://github.com/MiSTer-devel/SlugCross_MiSTer.git
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56 lines
1.6 KiB
Verilog
56 lines
1.6 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 12/01/2018 06:21:50 PM
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// Design Name:
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// Module Name: TopStateMachine
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module TopStateMachine(
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input clk,
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input btnUDLR,
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input btnC,
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input WinDetect,
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input LossDetect,
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output reset,
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output btnCenable,
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output btnUDLRenable,
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output TimerEnable,
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output flashSlug,
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output flashBorder,
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output [3:0] state
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);
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wire [3:0] Q;
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wire [3:0] D;
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TopStateMachineLogic TopStateMachineLogic (.clk(clk), .btnUDLR(btnUDLR), .btnC(btnC), .WinDetect(WinDetect), .LossDetect(LossDetect), .Q(Q), .reset(reset),
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.btnCenable(btnCenable), .btnUDLRenable(btnUDLRenable), .TimerEnable(TimerEnable), .flashSlug(flashSlug),
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.flashBorder(flashBorder), .D(D));
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FDRE #(.INIT(1'b1)) Q0_FF (.C(clk), .CE(1'b1), .D(D[0]), .Q(Q[0]));
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FDRE #(.INIT(1'b0)) Q1_FF (.C(clk), .CE(1'b1), .D(D[1]), .Q(Q[1]));
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FDRE #(.INIT(1'b0)) Q2_FF (.C(clk), .CE(1'b1), .D(D[2]), .Q(Q[2]));
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FDRE #(.INIT(1'b0)) Q3_FF (.C(clk), .CE(1'b1), .D(D[3]), .Q(Q[3]));
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assign state[0] = Q[0];
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assign state[1] = Q[1];
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assign state[2] = Q[2];
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assign state[3] = Q[3];
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endmodule
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