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https://github.com/MiSTer-devel/SlugCross_MiSTer.git
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118 lines
4.9 KiB
Verilog
118 lines
4.9 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 11/26/2018 01:44:01 PM
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// Design Name:
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// Module Name: TopLevel
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module TopLevel(
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input clkin,
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input clk,
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input btnU,
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input btnD,
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input btnL,
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input btnR,
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input btnC,
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input [15:0] sw,
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output Hsync,
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output Vsync,
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output [3:0] vgaRed,
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output [3:0] vgaBlue,
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output [3:0] vgaGreen,
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output [6:0] seg,
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output dp,
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output [3:0] an,
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output VBlank,
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output HBlank
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);
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wire digsel, frame, qsec;
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wire secEdge, flashOutSlug, flashOutBorder;
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wire btnCenable, btnUDLRenable, TimerEnable, resetTimer, LossDetect, WinDetect, flashSlug, flashBorder;
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wire [9:0] Hcount, Vcount;
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wire [3:0] BlueIn, GreenIn, RedIn, selInput, segInput, HorizRedOut, VertRedOut, HorizRedIn, VertRedIn, secOut;
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wire [15:0] timerOut;
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wire [9:0] SecOutSlug;
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assign digsel = 1;
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TopStateMachine TopStateMachine (.clk(clk), .btnUDLR(btnU | btnR | btnD | btnL), .btnC(btnC), .WinDetect(WinDetect), .LossDetect(LossDetect), .reset(resetTimer),
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.btnCenable(btnCenable), .btnUDLRenable(btnUDLRenable), .TimerEnable(TimerEnable), .flashSlug(flashSlug), .flashBorder(flashBorder));
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LossDetector LossDetector (.Green(GreenIn), .Red(HorizRedOut | VertRedOut), .LossDetect(LossDetect));
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WinDetector WinDetector (.Green(GreenIn), .Hcount(Hcount), .Vcount(Vcount), .WinDetect(WinDetect));
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//lab7_clks not_so_slow (.clkin(clkin), .greset(sw[0]), .clk(clk), .digsel(digsel));
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VGAController VGAController(.clk(clk), .RedIn(HorizRedOut | VertRedOut), .BlueIn({(BlueIn[3] & ~flashOutBorder),(BlueIn[2] & ~flashOutBorder), (BlueIn[1] & ~flashOutBorder), (BlueIn[0] & ~flashOutBorder)}), .GreenIn({(GreenIn[3] & ~flashOutSlug),(GreenIn[2] & ~flashOutSlug), (GreenIn[1] & ~flashOutSlug), (GreenIn[0] & ~flashOutSlug)}), .Hsync(Hsync), .Vsync(Vsync),
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.vgaRed(vgaRed), .vgaBlue(vgaBlue), .vgaGreen(vgaGreen), .VBlank(VBlank), .HBlank(HBlank), .Hcount(Hcount), .Vcount(Vcount), .frame(frame));
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BorderGenerator BorderGenerator (.Hcount(Hcount), .Vcount(Vcount), .Blue({BlueIn[3:0]}), .flash(flashBorder), .sec(~qsec));
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SlugGenerator SlugGenerator (.btnU(btnU & btnUDLRenable), .btnD(btnD & btnUDLRenable), .btnL(btnL & btnUDLRenable) , .btnR(btnR & btnUDLRenable), .reset(btnC & btnCenable), .frame(frame), .clk(clk),
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.Hcount(Hcount[9:0]), .Vcount(Vcount[9:0]), .Green({GreenIn[3:0]}), .flash(flashSlug), .sec(~qsec));
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VerticalObstacles VerticalObstacles (.Hcount(Hcount[9:0]), .Vcount(Vcount[9:0]), .Red(VertRedIn));
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VerticalGaps VerticalGaps (.Hcount(Hcount), .Vcount(Vcount), .clk(clk), .frame(frame), .btnC(btnC & btnCenable), .btnUDLR((btnU | btnR | btnD | btnL) & btnUDLRenable),
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.sw({sw[6], sw[5], sw[4]}), .RedIn(VertRedIn), .RedOut(VertRedOut), .Green(GreenIn), .sec(qsec));
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HorizontalObstacles HorizontalObstacles (.Hcount(Hcount[9:0]), .Vcount(Vcount[9:0]), .Red(HorizRedIn));
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HorizontalGaps HorizontalGaps (.Hcount(Hcount), .Vcount(Vcount), .clk(clk), .frame(frame), .btnC(btnC & btnCenable), .btnUDLR((btnU | btnR | btnD | btnL) & btnUDLRenable),
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.sw({sw[6], sw[5], sw[4]}), .RedIn(HorizRedIn), .RedOut(HorizRedOut), .Green(GreenIn), .sec(qsec));
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qsecTicker qsecTicker (.clk(clk), .frame(frame), .reset(1'b0), .qsec(qsec));
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Timer Timer (.clk(clk), .frame(frame), .CE(TimerEnable), .reset(resetTimer), .Q(timerOut[15:0]));
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RingCounter RingCounter(.advance(digsel), .clkin(clk), .Q(selInput));
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Selector Selector(.sel(selInput), .N(timerOut[15:0]), .H(segInput));
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hex7seg hex7seg(.n(segInput), .e(1'b1), .seg(seg));
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EdgeDetector SecEdge (.btn(~qsec), .clkin(clk), .out(secEdge));
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countU10 secGenerator(.clk(clk), .Up(secEdge), .Q(SecOutSlug));
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FlashModule SlugFlasher (.flash(flashSlug), .sec(SecOutSlug[0]), .flashOut(flashOutSlug));
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FlashModule BorderFlasher (.flash(flashBorder), .sec(SecOutSlug[0]), .flashOut(flashOutBorder));
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assign an[3] =(~selInput[3]) ;
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assign an[2] =(~selInput[2]) ;
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assign an[1] =(~selInput[1]) ;
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assign an[0] =(~selInput[0]) ;
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assign dp = (~selInput[2]);
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endmodule
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module FDRE(
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input R, CE, D, C,
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output reg Q
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);
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parameter INIT = 0;
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initial begin
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Q <= INIT;
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end
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always @(posedge C)
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if(R)
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Q <= 0;
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else if(CE)
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Q <= D;
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endmodule |