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35 lines
841 B
Verilog
35 lines
841 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 11/29/2018 03:40:57 PM
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// Design Name:
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// Module Name: SlugRedDetect
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module SlugRedDetect(
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input [3:0] Red,
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input [9:0] LowerRange,
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input [9:0] UpperRange,
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input [9:0] Hcount,
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input [3:0] Green,
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output SlugRedDetect
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);
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assign SlugRedDetect = (LowerRange <= Hcount) & (Hcount <= UpperRange) & (Green[3] & Red[3]) & (Green[2] & Red[2]) & (Green[1] & Red[1]) & (Green[0] & Red[0]);
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endmodule
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