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47 lines
1.3 KiB
Verilog
47 lines
1.3 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 11/29/2018 01:21:31 PM
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// Design Name:
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// Module Name: GapStateMachine
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module GapStateMachine(
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input clk,
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input btnUDLR,
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input btnC,
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input GapWallDetect,
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input SlugRedDetect,
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output load,
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output reset,
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output dir1,
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output dir2,
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output flash
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);
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wire [3:0] Q;
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wire [3:0] D;
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GapStateMachineLogic GapStateMachineLogic(.btnUDLR(btnUDLR), .btnC(btnC), .GapWallDetect(GapWallDetect), .SlugRedDetect(SlugRedDetect),
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.load(load), .reset(reset), .dir1(dir1), .dir2(dir2), .flash(flash), .Q(Q), .D(D));
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FDRE #(.INIT(1'b1)) Q0_FF (.C(clk), .CE(1'b1), .D(D[0]), .Q(Q[0]));
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FDRE #(.INIT(1'b0)) Q1_FF (.C(clk), .CE(1'b1), .D(D[1]), .Q(Q[1]));
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FDRE #(.INIT(1'b0)) Q2_FF (.C(clk), .CE(1'b1), .D(D[2]), .Q(Q[2]));
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FDRE #(.INIT(1'b0)) Q3_FF (.C(clk), .CE(1'b1), .D(D[3]), .Q(Q[3]));
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endmodule
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