mirror of
https://github.com/MiSTer-devel/QL_MiSTer.git
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fde2624b81
Main changes: 1) Improve accuracy of ZX8301 bus contention logic, including adding a wait cycle for writes and reducing the amount of ZX8301 bus access during VBLANK. 2) Add wait states to simulate extra bus access by 68008 for 16 bit ROM access. 3) Reworked IPC communication logic in ZX8302 and added a COMDATA latch.
101 lines
2.2 KiB
Systemverilog
101 lines
2.2 KiB
Systemverilog
// QL RAM timing simulation
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//
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// Copyright (C) 2019 Marcel Kilgus
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// Copyright (c) 2021 Daniele Terdina
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//
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// Much of the original QL RAM is used to generate the video signal. This module tries to slow
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// down the SDRAM access similarly to the original timing
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module ql_timing
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(
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input clk_sys,
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input reset,
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input enable,
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input ce_bus_p,
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input VBlank,
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input cpu_uds,
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input cpu_lds,
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input cpu_rw,
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input cpu_rom,
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output reg ram_delay_dtack
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);
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reg [5:0] chunk; // We got 40 chunks per display line...
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reg [3:0] chunkCycle; // ...with 12 cycles per chunk
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wire [5:0] num_busy_chunks = VBlank ? 6'd8 : 6'd32; // 32 chunks used by ZX8301 for video, 8 during vblank for RAM refresh
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wire could_start = chunk >= num_busy_chunks || chunkCycle == 4'd0; // For used chunks, the CPU can only access RAM in-between
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wire ds;
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assign ds = cpu_uds || cpu_lds;
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reg prev_ds;
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reg [2:0] dtack_count;
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reg extra_access;
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always @(posedge clk_sys)
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begin
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if (reset || !enable)
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begin
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chunk <= 0;
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chunkCycle <= 0;
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ram_delay_dtack <= 0;
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end
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else
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begin
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if (ce_bus_p)
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begin
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chunkCycle <= chunkCycle + 4'd1;
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if (chunkCycle == 4'd11)
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begin
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chunkCycle <= 4'd0;
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if (chunk == 6'd39)
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chunk <= 6'd0;
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else
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chunk <= chunk + 6'd1;
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end
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if (ds && ~prev_ds)
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begin
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// New bus access. ZX8301 takes about 1 cycle before deciding whether to insert wait states.
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// ZX8301 only checks DS and not AS... as a result, at least one wait state is inserted for all writes.
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ram_delay_dtack <= 1;
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dtack_count <= 3'd1;
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extra_access <= cpu_uds && cpu_lds; // 16bit access?
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end
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else
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begin
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if (dtack_count == 3'd1 && ram_delay_dtack)
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begin
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if (could_start || cpu_rom)
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begin
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if (extra_access)
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begin
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// For 16 bit access, add wait states to simulate the time it takes the 68008
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// to complete a second bus access
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dtack_count <= cpu_rw ? 3'd4 : 3'd5;
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extra_access <= 0;
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end
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else
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begin
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ram_delay_dtack <= 0;
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end
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end
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end
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else
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begin
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dtack_count <= dtack_count - 3'd1;
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end
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end
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prev_ds <= ds;
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end
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end
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end
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endmodule |