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https://github.com/MiSTer-devel/QL_MiSTer.git
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183 lines
5.2 KiB
Verilog
183 lines
5.2 KiB
Verilog
//
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// mdv.v - Microdrive
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//
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// Sinclair QL for the MiST
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// https://github.com/mist-devel
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//
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// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module mdv
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(
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input clk, // System clock (84mHz)
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input ce, // CPU clock
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input reset,
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input reverse,
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input sel,
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// control bits
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output gap,
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output tx_empty,
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output rx_ready,
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output [7:0] dout,
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// ram interface to read image
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input download,
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input [16:0] dl_addr,
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input [15:0] dl_data,
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input dl_wr
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);
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reg [16:0] mem_addr;
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wire [15:0] mdv_din;
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dpram #(17, 88000) vram
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(
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.wrclock(clk),
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.wraddress(dl_addr),
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.wren(dl_wr),
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.byteena_a(2'b11),
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.data(dl_data),
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.rdclock(clk),
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.rdaddress(mem_addr),
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.q(mdv_din)
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);
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// a gap is permanently present if no mdv is inserted or if
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// there's a gap on the inserted one. This is the signal that triggers
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// the irq and can be seen by the cpu
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assign gap = (!mdv_present) || mdv_gap /* synthesis keep */;
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// the mdv_rx_ready flag must be quite short as the CPU never waist for it to end
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wire mdv_valid = (mdv_bit_cnt[2:0] == 2);
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assign rx_ready = mdv_present && mdv_data_valid && mdv_valid;
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assign tx_empty = 1'b0;
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// microdrive implementation works with images which are uploaded by the user into
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// the BRAM. It is then continously replayed from there at 200kbit/s
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// determine mdv image size after download
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reg [16:0] mdv_end;
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always @(posedge clk or posedge reset) begin
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if(reset) mdv_end <= 0;
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else begin
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if(dl_wr) mdv_end <= dl_addr;
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end
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end
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// the microdrive at 200kbit/s reads a bit every 8.3us and needs a new word
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// every 80us.
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// gaps are 2800/3400 us which is 35 words at 200kbit/s
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assign dout = mdv_bit_cnt[3]?mdv_data[7:0]:mdv_data[15:8];
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// a microdrive image is present if at least one word is in the buffer
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wire mdv_present = sel && (mdv_end != 0);
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reg [3:0] mdv_bit_cnt /* synthesis noprune */;
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// also generate gap timing
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reg [15:0] mdv_data;
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reg mdv_data_valid;
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reg mdv_gap;
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// microdrive clock runs at 200khz
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// -> new word required every 80us
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localparam mdv_clk_scaler = 7500000/(200000)-1;
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always @(posedge clk) begin
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reg [9:0] mdv_gap_cnt;
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reg mdv_gap_state;
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reg mdv_gap_active;
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reg [7:0] mdv_clk_cnt;
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if(download) begin
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mem_addr <= 0;
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// assume we start at the end of a post-sector/pre-header gap
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mdv_gap_cnt <= 10'd0; // count bytes until gap
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mdv_gap_state <= 1'b1; // toggle header + data gap
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mdv_gap_active <= 1'b1; // gap atm
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mdv_gap <= 1'b1;
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end
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if(ce) begin
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if(mdv_clk_cnt == mdv_clk_scaler) mdv_clk_cnt <= 0;
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else mdv_clk_cnt <= mdv_clk_cnt + 1'd1;
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if(!mdv_clk_cnt) begin
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mdv_bit_cnt <= mdv_bit_cnt + 4'd1;
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if(mdv_bit_cnt == 15) begin
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mdv_data <= mdv_din;
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mdv_data_valid <= !mdv_gap_active && (mdv_gap_cnt > 5) && !(mdv_gap_state && (mdv_gap_cnt > 7) && (mdv_gap_cnt < 12));
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// reset counters when address is out of range
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if(mem_addr > mdv_end) begin
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mem_addr <= 0;
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// assume we start at the end of a post-sector/pre-header gap
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mdv_gap_cnt <= 10'd0; // count bytes until gap
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mdv_gap_state <= 1'b1; // toggle header + data gap
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mdv_gap_active <= 1'b1; // gap atm
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mdv_gap <= 1'b1;
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end else begin
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mdv_gap_cnt <= mdv_gap_cnt + 10'd1;
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if(mdv_gap_active) begin
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// stop sending gap after 35 words = 70 bytes = 2800us
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if(mdv_gap_cnt == 34) begin
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mdv_gap_cnt <= 10'd0; // restart counter until next gap
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mdv_gap_active <= 1'b0; // no gap anymore
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mdv_gap_state <= !mdv_gap_state; // toggle gap/data
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mdv_gap <= 1'b0;
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end
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end else begin
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mem_addr <= mem_addr + 1'd1;
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if((!mdv_gap_state) && (mdv_gap_cnt == 13)) begin
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// done reading 14 words header data
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mdv_gap_cnt <= 10'd0; // restart counter for gap
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mdv_gap_active <= 1'b1; // now comes a gap
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mdv_gap <= 1'b1;
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end else if(mdv_gap_state && (mdv_gap_cnt == 328)) begin
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// done reading 330 words sector data
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mdv_gap_cnt <= 10'd0; // restart counter for gap
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mdv_gap_active <= 1'b1; // now comes a gap
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mdv_gap <= 1'b1;
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if(reverse) begin
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// The sectors on cartridges are written in descending order
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// Some images seem to contain them in ascending order. So we
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// have to replay them backwards for better performance
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if(mem_addr == 343 - 1)
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mem_addr <= mdv_end - 17'd343 + 1'd1;
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else
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mem_addr <= mem_addr - 17'd686 + 1'd1;
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end
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end
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end
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end
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end
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end
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end
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end
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endmodule
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