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60 lines
1.7 KiB
Verilog
60 lines
1.7 KiB
Verilog
module dpram #(parameter ADDRWIDTH=0, NUMWORDS=1<<ADDRWIDTH)
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(
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input wrclock,
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input [ADDRWIDTH-1:0] wraddress,
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input wren,
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input [1:0] byteena_a,
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input [15:0] data,
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input rdclock,
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input [ADDRWIDTH-1:0] rdaddress,
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output [15:0] q
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);
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altsyncram altsyncram_component (
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.address_a (wraddress),
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.address_b (rdaddress),
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.byteena_a (byteena_a),
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.clock0 (wrclock),
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.clock1 (rdclock),
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.data_a (data),
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.wren_a (wren),
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.q_b (q),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_b (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b ({16{1'b1}}),
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.eccstatus (),
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.q_a (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_b (1'b0));
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defparam
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altsyncram_component.address_aclr_b = "NONE",
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altsyncram_component.address_reg_b = "CLOCK1",
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altsyncram_component.byte_size = 8,
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_input_b = "BYPASS",
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altsyncram_component.clock_enable_output_b = "BYPASS",
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altsyncram_component.intended_device_family = "Cyclone V",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = NUMWORDS,
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altsyncram_component.numwords_b = NUMWORDS,
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altsyncram_component.operation_mode = "DUAL_PORT",
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altsyncram_component.outdata_aclr_b = "NONE",
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altsyncram_component.outdata_reg_b = "UNREGISTERED",
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.widthad_a = ADDRWIDTH,
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altsyncram_component.widthad_b = ADDRWIDTH,
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altsyncram_component.width_a = 16,
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altsyncram_component.width_b = 16,
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altsyncram_component.width_byteena_a = 2;
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endmodule
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