mirror of
https://github.com/MiSTer-devel/PokemonMini_MiSTer.git
synced 2026-04-26 03:04:36 +00:00
257 lines
10 KiB
Tcl
257 lines
10 KiB
Tcl
derive_pll_clocks
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derive_clock_uncertainty
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# core specific constraints
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# Search "---customize here---" for the few decisions you need to make
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#
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# By default, the most challenging timing spec is applied to work in
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# many JTAG chain setup situations
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set_time_format -unit ns -decimal_places 3
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# This is the main entry point called at the end of this SDC file.
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proc set_jtag_timing_constraints { } {
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# If the timing characteristic outside of FPGA is well understood, and
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# there is a need to provide more slack to allow flexible placement of
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# JTAG logic in the FPGA core, use the timing constraints for both
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# timing analysis and fitter; otherwise, use the default fitter timing
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# constraints.
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# ---customize here---
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set use_fitter_specific_constraint 0
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if { $use_fitter_specific_constraint && [string equal quartus_fit $::TimeQuestInfo(nameofexecutable)] } {
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# Define a different set of timing spec to influence place-and-route
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# result in the jtag clock domain. The slacks outside of FPGA are
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# maximized.
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set_default_quartus_fit_timing_directive
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} else {
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# Define a set of timing constraints that describe the JTAG paths
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# for the Timing Analyzer to analyze. The Timing Analyzer timing reports show whether
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# the JTAG logic in the FPGA core will operates in this setup.
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set_jtag_timing_spec_for_timing_analysis
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}
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}
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proc set_default_quartus_fit_timing_directive { } {
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# A10 supports max 33.3Mhz clock
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set jtag_33Mhz_t_period 30
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create_clock -name {altera_reserved_tck} -period $jtag_33Mhz_t_period [get_ports {altera_reserved_tck}]
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set_clock_groups -asynchronous -group {altera_reserved_tck}
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# Force fitter to place register driving TDO pin to be as close to
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# the JTAG controller as possible to maximize the slack outside of FPGA.
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set_max_delay -to [get_ports { altera_reserved_tdo } ] 0
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}
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proc set_jtag_timing_spec_for_timing_analysis { } {
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derive_clock_uncertainty
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# There are few possible JTAG chain configurations:
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# a. This device is the only device in the JTAG chain
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# b. This device is the first one in the JTAG chain
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# c. This device is in the middle of the JTAG chain
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# d. This device is the last one in the JTAG chain
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# No matter where the device is in the chain. The tck and tms are driven
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# directly from JTAG hardware.
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set_tck_timing_spec
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set_tms_timing_spec
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# Depending on where the device is located along the chain, tdi can be
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# either driven by blaster hw (a. b.) or driven by another device in the
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# chain(c. d.)
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# ---customize here---
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set tdi_is_driven_by_blaster 1
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if { $tdi_is_driven_by_blaster } {
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set_tdi_timing_spec_when_driven_by_blaster
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} else {
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set_tdi_timing_spec_when_driven_by_device
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}
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# Depending on where the device is located along the chain, tdo can
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# drive either blaster hw (a. d.) or another device in the chain (b. c.)
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# ---customize here---
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set tdo_drive_blaster 1
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if { $tdo_drive_blaster } {
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set_tdo_timing_spec_when_drive_blaster
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} else {
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set_tdo_timing_spec_when_drive_device
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}
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set_optional_ntrst_timing_spec
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# Cut a few timing paths that are not related to JTAG logic in
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# the FPGA core, such as security mode.
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set_false_path -from [get_ports {altera_reserved_tdi}] -to [get_ports {altera_reserved_tdo}]
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if { [get_collection_size [get_registers -nowarn *~jtag_reg]] > 0 } {
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set_false_path -from [get_registers *~jtag_reg] -to [get_ports {altera_reserved_tdo}]
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}
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}
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proc set_tck_timing_spec { } {
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# USB Blaster 1 uses 6 MHz clock = 166.666 ns period
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set ub1_t_period 166.666
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# USB Blaster 2 uses 24 MHz clock = 41.666 ns period
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set ub2_default_t_period 41.666
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# USB Blaster 2 running at 16 MHz clock safe mode = 62.5 ns period
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set ub2_safe_t_period 62.5
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# ---customize here---
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set tck_t_period $ub2_default_t_period
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create_clock -name {altera_reserved_tck} -period $tck_t_period [get_ports {altera_reserved_tck}]
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set_clock_groups -asynchronous -group {altera_reserved_tck}
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}
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proc get_tck_delay_max { } {
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set tck_blaster_tco_max 14.603
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set tck_cable_max 11.627
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# tck delay on the PCB depends on the trace length from JTAG 10-pin
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# header to FPGA on board. In general on the PCB, the signal travels
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# at the speed of ~160 ps/inch (1000 mils = 1 inch).
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# ---customize here---
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set tck_header_trace_max 0.5
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return [expr $tck_blaster_tco_max + $tck_cable_max + $tck_header_trace_max]
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}
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proc get_tck_delay_min { } {
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set tck_blaster_tco_min 14.603
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set tck_cable_min 10.00
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# tck delay on the PCB depends on the trace length from JTAG 10-pin
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# header to FPGA on board. In general on the PCB, the signal travels
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# at the speed of ~160 ps/inch (1000 mils = 1 inch).
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# ---customize here---
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set tck_header_trace_min 0.1
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return [expr $tck_blaster_tco_min + $tck_cable_min + $tck_header_trace_min]
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}
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proc set_tms_timing_spec { } {
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set tms_blaster_tco_max 9.468
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set tms_blaster_tco_min 9.468
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set tms_cable_max 11.627
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set tms_cable_min 10.0
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# tms delay on the PCB depends on the trace length from JTAG 10-pin
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# header to FPGA on board. In general on the PCB, the signal travels
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# at the speed of ~160 ps/inch (1000 mils = 1 inch).
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# ---customize here---
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set tms_header_trace_max 0.5
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set tms_header_trace_min 0.1
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set tms_in_max [expr $tms_cable_max + $tms_header_trace_max + $tms_blaster_tco_max - [get_tck_delay_min]]
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set tms_in_min [expr $tms_cable_min + $tms_header_trace_min + $tms_blaster_tco_min - [get_tck_delay_max]]
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set_input_delay -add_delay -clock_fall -clock altera_reserved_tck -max $tms_in_max [get_ports {altera_reserved_tms}]
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set_input_delay -add_delay -clock_fall -clock altera_reserved_tck -min $tms_in_min [get_ports {altera_reserved_tms}]
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}
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proc set_tdi_timing_spec_when_driven_by_blaster { } {
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set tdi_blaster_tco_max 8.551
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set tdi_blaster_tco_min 8.551
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set tdi_cable_max 11.627
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set tdi_cable_min 10.0
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# tms delay on the PCB depends on the trace length from JTAG 10-pin
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# header to FPGA on board. In general on the PCB, the signal travels
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# at the speed of ~160 ps/inch (1000 mils = 1 inch).
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# ---customize here---
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set tdi_header_trace_max 0.5
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set tdi_header_trace_min 0.1
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set tdi_in_max [expr $tdi_cable_max + $tdi_header_trace_max + $tdi_blaster_tco_max - [get_tck_delay_min]]
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set tdi_in_min [expr $tdi_cable_min + $tdi_header_trace_min + $tdi_blaster_tco_min - [get_tck_delay_max]]
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#TDI launches at the falling edge of TCK per standard
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set_input_delay -add_delay -clock_fall -clock altera_reserved_tck -max $tdi_in_max [get_ports {altera_reserved_tdi}]
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set_input_delay -add_delay -clock_fall -clock altera_reserved_tck -min $tdi_in_min [get_ports {altera_reserved_tdi}]
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}
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proc set_tdi_timing_spec_when_driven_by_device { } {
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# TCO timing spec of tdo on the device driving this tdi input
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# ---customize here---
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set previous_device_tdo_tco_max 10.0
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set previous_device_tdo_tco_min 10.0
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# tdi delay on the PCB depends on the trace length from JTAG 10-pin
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# header to FPGA on board. In general on the PCB, the signal travels
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# at the speed of ~160 ps/inch (1000 mils = 1 inch).
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# ---customize here---
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set tdi_trace_max 0.5
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set tdi_trace_min 0.1
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set tdi_in_max [expr $previous_device_tdo_tco_max + $tdi_trace_max - [get_tck_delay_min]]
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set tdi_in_min [expr $previous_device_tdo_tco_min + $tdi_trace_min - [get_tck_delay_max]]
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#TDI launches at the falling edge of TCK per standard
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set_input_delay -add_delay -clock_fall -clock altera_reserved_tck -max $tdi_in_max [get_ports {altera_reserved_tdi}]
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set_input_delay -add_delay -clock_fall -clock altera_reserved_tck -min $tdi_in_min [get_ports {altera_reserved_tdi}]
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}
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proc set_tdo_timing_spec_when_drive_blaster { } {
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set tdo_blaster_tsu 5.831
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set tdo_blaster_th -1.651
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set tdo_cable_max 11.627
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set tdo_cable_min 10.0
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# tdi delay on the PCB depends on the trace length from JTAG 10-pin
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# header to FPGA on board. In general on the PCB, the signal travels
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# at the speed of ~160 ps/inch (1000 mils = 1 inch).
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# ---customize here---
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set tdo_header_trace_max 0.5
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set tdo_header_trace_min 0.1
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set tdo_out_max [expr $tdo_cable_max + $tdo_header_trace_max + $tdo_blaster_tsu + [get_tck_delay_max]]
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set tdo_out_min [expr $tdo_cable_min + $tdo_header_trace_min - $tdo_blaster_th + [get_tck_delay_min]]
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#TDO does not latch inside the USB Blaster II at the rising edge of TCK,
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# it actually is latched one half cycle later in packed mode
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# (equivalent to 1 JTAG fall-to-fall cycles)
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set_output_delay -add_delay -clock_fall -clock altera_reserved_tck -max $tdo_out_max [get_ports {altera_reserved_tdo}]
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set_output_delay -add_delay -clock_fall -clock altera_reserved_tck -min $tdo_out_min [get_ports {altera_reserved_tdo}]
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}
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proc set_tdo_timing_spec_when_drive_device { } {
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# TCO timing spec of tdi on the device driven by this tdo output
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# ---customize here---
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set next_device_tdi_tco_max 10.0
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set next_device_tdi_tco_min 10.0
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# tdi delay on the PCB depends on the trace length from JTAG 10-pin
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# header to FPGA on board. In general on the PCB, the signal travels
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# at the speed of ~160 ps/inch (1000 mils = 1 inch).
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# ---customize here---
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set tdo_trace_max 0.5
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set tdo_trace_min 0.1
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set tdo_out_max [expr $next_device_tdi_tco_max + $tdo_trace_max + [get_tck_delay_max]]
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set tdo_out_min [expr $next_device_tdi_tco_min + $tdo_trace_min + [get_tck_delay_min]]
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#TDO latches at the rising edge of TCK per standard
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set_output_delay -add_delay -clock altera_reserved_tck -max $tdo_out_max [get_ports {altera_reserved_tdo}]
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set_output_delay -add_delay -clock altera_reserved_tck -min $tdo_out_min [get_ports {altera_reserved_tdo}]
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}
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proc set_optional_ntrst_timing_spec { } {
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# ntrst is an optional JTAG pin to asynchronously reset the device JTAG controller.
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# There is no path from this pin to any FPGA core fabric.
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if { [get_collection_size [get_ports -nowarn {altera_reserved_ntrst}]] > 0 } {
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set_false_path -from [get_ports {altera_reserved_ntrst}]
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}
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}
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set_jtag_timing_constraints
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