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https://github.com/MiSTer-devel/PSX_MiSTer.git
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ee819edee0
- Timer: reset TMR0 on falling HBlank instead of rising HBlank (fulfills HW test and improves Justifier in Area51)
348 lines
14 KiB
VHDL
348 lines
14 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity timer is
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port
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(
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clk1x : in std_logic;
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ce : in std_logic;
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reset : in std_logic;
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error : out std_logic;
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dotclock : in std_logic;
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hblank : in std_logic;
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vblank : in std_logic;
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irqRequest0 : out std_logic := '0';
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irqRequest1 : out std_logic := '0';
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irqRequest2 : out std_logic := '0';
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bus_addr : in unsigned(5 downto 0);
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bus_dataWrite : in std_logic_vector(31 downto 0);
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bus_read : in std_logic;
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bus_write : in std_logic;
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bus_dataRead : out std_logic_vector(31 downto 0);
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-- synthesis translate_off
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export_t_current0 : out unsigned(15 downto 0);
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export_t_current1 : out unsigned(15 downto 0);
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export_t_current2 : out unsigned(15 downto 0);
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-- synthesis translate_on
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loading_savestate : in std_logic;
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SS_reset : in std_logic;
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SS_DataWrite : in std_logic_vector(31 downto 0);
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SS_Adr : in unsigned(3 downto 0);
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SS_wren : in std_logic;
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SS_rden : in std_logic;
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SS_DataRead : out std_logic_vector(31 downto 0)
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);
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end entity;
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architecture arch of timer is
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type timerRecord is record
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T_CURRENT : unsigned(15 downto 0);
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T_MODE : unsigned(15 downto 0);
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T_TARGET : unsigned(15 downto 0);
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irqDone : std_logic;
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blockNext : std_logic;
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end record;
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type ttimerArray is array (0 to 2) of timerRecord;
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signal timerArray : ttimerArray := (others => ((others => '0'), (others => '0'), (others => '0'), '0', '0'));
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signal timer2_subcount : unsigned(2 downto 0);
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signal hblank_1 : std_logic;
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signal vblank_1 : std_logic;
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signal dotclock_1 : std_logic;
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-- savestates
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type t_ssarray is array(0 to 15) of std_logic_vector(31 downto 0);
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signal ss_out : t_ssarray := (others => (others => '0'));
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begin
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irqRequest0 <= not timerArray(0).T_MODE(10);
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irqRequest1 <= not timerArray(1).T_MODE(10);
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irqRequest2 <= not timerArray(2).T_MODE(10);
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-- synthesis translate_off
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export_t_current0 <= timerArray(0).T_CURRENT;
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export_t_current1 <= timerArray(1).T_CURRENT;
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export_t_current2 <= timerArray(2).T_CURRENT;
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-- synthesis translate_on
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ss_out(0)(15 downto 0) <= std_logic_vector(timerArray(0).T_CURRENT);
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ss_out(3)(15 downto 0) <= std_logic_vector(timerArray(0).T_MODE);
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ss_out(6)(15 downto 0) <= std_logic_vector(timerArray(0).T_TARGET);
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ss_out(9)(11) <= timerArray(0).irqDone;
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ss_out(1)(15 downto 0) <= std_logic_vector(timerArray(1).T_CURRENT);
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ss_out(4)(15 downto 0) <= std_logic_vector(timerArray(1).T_MODE);
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ss_out(7)(15 downto 0) <= std_logic_vector(timerArray(1).T_TARGET);
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ss_out(9)(12) <= timerArray(1).irqDone;
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ss_out(2)(15 downto 0) <= std_logic_vector(timerArray(2).T_CURRENT);
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ss_out(5)(15 downto 0) <= std_logic_vector(timerArray(2).T_MODE);
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ss_out(8)(15 downto 0) <= std_logic_vector(timerArray(2).T_TARGET);
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ss_out(9)(13) <= timerArray(2).irqDone;
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ss_out(9)(2 downto 0) <= std_logic_vector(timer2_subcount);
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process (clk1x)
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variable channel : integer range 0 to 3;
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variable newTick : std_logic_vector(2 downto 0);
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variable newIRQ : std_logic;
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begin
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if rising_edge(clk1x) then
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error <= '0';
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if (reset = '1') then
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if (loading_savestate = '0') then
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timerArray(0).T_CURRENT <= (others => '0');
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timerArray(0).T_MODE <= x"0400";
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timerArray(0).T_TARGET <= (others => '0');
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timerArray(0).irqDone <= '0';
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timerArray(1).T_CURRENT <= (others => '0');
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timerArray(1).T_MODE <= x"0400";
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timerArray(1).T_TARGET <= (others => '0');
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timerArray(1).irqDone <= '0';
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timerArray(2).T_CURRENT <= (others => '0');
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timerArray(2).T_MODE <= x"0400";
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timerArray(2).T_TARGET <= (others => '0');
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timerArray(2).irqDone <= '0';
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timer2_subcount <= (others => '0');
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end if;
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for i in 0 to 2 loop
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timerArray(i).blockNext <= '0';
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end loop;
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hblank_1 <= hblank;
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vblank_1 <= vblank;
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elsif (SS_wren = '1') then
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if (to_integer(SS_Adr) = 0) then timerArray(0).T_CURRENT <= unsigned(SS_DataWrite(15 downto 0)); end if;
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if (to_integer(SS_Adr) = 3) then timerArray(0).T_MODE <= unsigned(SS_DataWrite(15 downto 0)); end if;
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if (to_integer(SS_Adr) = 6) then timerArray(0).T_TARGET <= unsigned(SS_DataWrite(15 downto 0)); end if;
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if (to_integer(SS_Adr) = 9) then timerArray(0).irqDone <= SS_DataWrite(11); end if;
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if (to_integer(SS_Adr) = 1) then timerArray(1).T_CURRENT <= unsigned(SS_DataWrite(15 downto 0)); end if;
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if (to_integer(SS_Adr) = 4) then timerArray(1).T_MODE <= unsigned(SS_DataWrite(15 downto 0)); end if;
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if (to_integer(SS_Adr) = 7) then timerArray(1).T_TARGET <= unsigned(SS_DataWrite(15 downto 0)); end if;
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if (to_integer(SS_Adr) = 9) then timerArray(1).irqDone <= SS_DataWrite(12); end if;
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if (to_integer(SS_Adr) = 2) then timerArray(2).T_CURRENT <= unsigned(SS_DataWrite(15 downto 0)); end if;
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if (to_integer(SS_Adr) = 5) then timerArray(2).T_MODE <= unsigned(SS_DataWrite(15 downto 0)); end if;
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if (to_integer(SS_Adr) = 8) then timerArray(2).T_TARGET <= unsigned(SS_DataWrite(15 downto 0)); end if;
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if (to_integer(SS_Adr) = 9) then timerArray(2).irqDone <= SS_DataWrite(13); end if;
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if (to_integer(SS_Adr) = 9) then timer2_subcount <= unsigned(SS_DataWrite(2 downto 0)); end if;
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elsif (ce = '1') then
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timer2_subcount <= timer2_subcount + 1;
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hblank_1 <= hblank;
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vblank_1 <= vblank;
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dotclock_1 <= dotclock;
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for i in 0 to 2 loop
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if (timerArray(i).T_MODE(7) = '0') then -- not toggle mode -> reset irq
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timerArray(i).T_MODE(10) <= '1';
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end if;
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end loop;
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-- check for new ticks
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newTick := "000";
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if (timerArray(0).T_MODE(8) = '1') then
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newTick(0) := dotclock and (not dotclock_1);
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else
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newTick(0) := '1';
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end if;
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if (timerArray(1).T_MODE(8) = '1') then
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if (hblank_1 = '0' and hblank = '1') then -- todo: correct hblank timer tick position to be found
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newTick(1) := '1';
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end if;
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else
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newTick(1) := '1';
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end if;
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if (timerArray(2).T_MODE(9) = '1') then
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if (timer2_subcount = "111") then
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newTick(2) := '1';
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end if;
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else
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newTick(2) := '1';
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end if;
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-- filter ticks with sync mode
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if (timerArray(0).T_MODE(0) = '1') then
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case (timerArray(0).T_MODE(2 downto 1)) is
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when "00" => if (hblank = '1') then newTick(0) := '0'; end if;
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when "10" => if (hblank = '0') then newTick(0) := '0'; end if;
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when "11" => newTick(0) := '0';
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when others => null;
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end case;
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end if;
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if (timerArray(1).T_MODE(0) = '1') then
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case (timerArray(1).T_MODE(2 downto 1)) is
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when "00" => if (vblank = '1') then newTick(1) := '0'; end if;
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when "10" => if (vblank = '0') then newTick(1) := '0'; end if;
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when "11" => newTick(1) := '0';
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when others => null;
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end case;
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end if;
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if (timerArray(2).T_MODE(0) = '1') then
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case (timerArray(2).T_MODE(2 downto 1)) is
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when "00" => newTick(2) := '0';
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when "11" => newTick(2) := '0';
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when others => null;
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end case;
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end if;
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-- apply ticks
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for i in 0 to 2 loop
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timerArray(i).blockNext <= '0';
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if (newTick(i) = '1' and timerArray(i).blockNext = '0') then
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timerArray(i).T_CURRENT <= timerArray(i).T_CURRENT + 1;
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newIRQ := '0';
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if (timerArray(i).T_CURRENT = timerArray(i).T_TARGET) then
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timerArray(i).T_MODE(11) <= '1';
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if (timerArray(i).T_MODE(4) = '1') then
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newIRQ := '1';
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end if;
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if (timerArray(i).T_MODE(3) = '1') then
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timerArray(i).T_CURRENT <= (others => '0');
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timerArray(i).blockNext <= '1';
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end if;
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end if;
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if (timerArray(i).T_CURRENT = x"FFFF") then
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timerArray(i).T_MODE(12) <= '1';
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if (timerArray(i).T_MODE(5) = '1') then
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newIRQ := '1';
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end if;
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end if;
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if (timerArray(i).irqDone = '1' and timerArray(i).T_MODE(6) = '0') then
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newIRQ := '0';
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end if;
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if (newIRQ = '1') then
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timerArray(i).irqDone <= '1';
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if (timerArray(i).T_MODE(7) = '1') then -- toggle mode
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timerArray(i).T_MODE(10) <= not timerArray(i).T_MODE(10);
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else
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timerArray(i).T_MODE(10) <= '0';
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end if;
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end if;
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end if;
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end loop;
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-- apply resets
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if (timerArray(0).T_MODE(0) = '1') then
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if (timerArray(0).T_MODE(2 downto 1) = "01" or timerArray(0).T_MODE(2 downto 1) = "10") then
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if (hblank_1 = '1' and hblank = '0') then
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timerArray(0).T_CURRENT <= (others => '0');
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end if;
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end if;
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if (timerArray(0).T_MODE(2 downto 1) = "11") then
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if (hblank_1 = '1' and hblank = '0') then
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timerArray(0).T_MODE(0) <= '0';
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end if;
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end if;
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end if;
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if (timerArray(1).T_MODE(0) = '1') then
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if (timerArray(1).T_MODE(2 downto 1) = "01" or timerArray(1).T_MODE(2 downto 1) = "10") then
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if (vblank_1 = '0' and vblank = '1') then
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timerArray(1).T_CURRENT <= (others => '0');
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end if;
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end if;
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if (timerArray(1).T_MODE(2 downto 1) = "11") then
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if (vblank_1 = '0' and vblank = '1') then
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timerArray(1).T_MODE(0) <= '0';
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end if;
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end if;
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end if;
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-- bus interface
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bus_dataRead <= (others => '0');
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channel := to_integer(unsigned(bus_addr(5 downto 4)));
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-- bus read
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if (bus_read = '1') then
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bus_dataRead <= (others => '1');
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if (channel < 3) then
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case (bus_addr(3 downto 0)) is
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when x"0" => bus_dataRead <= x"0000" & std_logic_vector(timerArray(channel).T_CURRENT);
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when x"4" =>
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bus_dataRead <= x"0000" & std_logic_vector(timerArray(channel).T_MODE);
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timerArray(channel).T_MODE(12 downto 11) <= "00";
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when x"8" => bus_dataRead <= x"0000" & std_logic_vector(timerArray(channel).T_TARGET);
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when others => null;
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end case;
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end if;
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end if;
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-- bus write
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if (bus_write = '1') then
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if (channel < 3) then
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case (bus_addr(3 downto 0)) is
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when x"0" =>
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timerArray(channel).T_CURRENT <= unsigned(bus_dataWrite(15 downto 0));
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timerArray(channel).blockNext <= '1';
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when x"4" =>
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timerArray(channel).T_MODE( 9 downto 0) <= unsigned(bus_dataWrite( 9 downto 0));
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timerArray(channel).T_MODE(15 downto 13) <= unsigned(bus_dataWrite(15 downto 13));
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timerArray(channel).irqDone <= '0';
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timerArray(channel).T_CURRENT <= (others => '0');
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timerArray(channel).blockNext <= '1';
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when x"8" => timerArray(channel).T_TARGET <= unsigned(bus_dataWrite(15 downto 0));
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when others => null;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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--##############################################################
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--############################### savestates
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--##############################################################
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process (clk1x)
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begin
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if (rising_edge(clk1x)) then
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if (SS_rden = '1') then
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SS_DataRead <= ss_out(to_integer(SS_Adr));
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end if;
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end if;
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end process;
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end architecture;
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