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af2a41033e
- GPU: always generate 263 hblank timer signals per NTSC frame, even in interlaced mode(fixes Turbo Prop Racing)
88 lines
3.2 KiB
VHDL
88 lines
3.2 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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package pGPU is
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type div_type is record
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start : std_logic;
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done : std_logic;
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dividend : signed(44 downto 0);
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divisor : signed(24 downto 0);
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quotient : signed(44 downto 0);
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remainder : signed(24 downto 0);
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end record;
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type tvideoout_settings is record
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GPUSTAT_VerRes : std_logic;
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GPUSTAT_PalVideoMode : std_logic;
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GPUSTAT_VertInterlace : std_logic;
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GPUSTAT_HorRes2 : std_logic;
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GPUSTAT_HorRes1 : std_logic_vector(1 downto 0);
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GPUSTAT_ColorDepth24 : std_logic;
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GPUSTAT_DisplayDisable : std_logic;
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vramRange : unsigned(18 downto 0);
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hDisplayRange : unsigned(23 downto 0);
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vDisplayRange : unsigned(19 downto 0);
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pal60 : std_logic;
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syncInterlace : std_logic;
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rotate180 : std_logic;
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fixedVBlank : std_logic;
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vCrop : std_logic_vector(1 downto 0);
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hCrop : std_logic;
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dither24 : std_logic;
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render24 : std_logic;
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end record;
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type tvideoout_reports is record
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vsync : std_logic;
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irq_VBLANK : std_logic;
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hblank_tmr : std_logic;
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GPUSTAT_InterlaceField : std_logic;
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GPUSTAT_DrawingOddline : std_logic;
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inVsync : std_logic;
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interlacedDisplayField : std_logic;
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activeLineLSB : std_logic;
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dotclock : std_logic;
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end record;
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type tvideoout_ss is record
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interlacedDisplayField : std_logic;
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nextHCount : std_logic_vector(11 downto 0);
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vpos : std_logic_vector(8 downto 0);
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vdisp : std_logic_vector(8 downto 0);
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inVsync : std_logic;
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activeLineLSB : std_logic;
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GPUSTAT_InterlaceField : std_logic;
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GPUSTAT_DrawingOddline : std_logic;
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end record;
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type tvideoout_request is record
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fetch : std_logic;
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fetchsize : unsigned(9 downto 0);
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lineInNext : unsigned(8 downto 0);
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xpos : integer range 0 to 1023;
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lineDisp : unsigned(8 downto 0);
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end record;
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type tvideoout_out is record
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hsync : std_logic;
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vsync : std_logic;
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hblank : std_logic;
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vblank : std_logic;
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DisplayWidth : unsigned(10 downto 0);
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DisplayHeight : unsigned( 9 downto 0);
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DisplayWidthReal : unsigned(10 downto 0);
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DisplayHeightReal : unsigned( 9 downto 0);
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DisplayOffsetX : unsigned( 9 downto 0);
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DisplayOffsetY : unsigned( 8 downto 0);
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ce : std_logic;
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interlace : std_logic;
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r : std_logic_vector(7 downto 0);
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g : std_logic_vector(7 downto 0);
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b : std_logic_vector(7 downto 0);
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isPal : std_logic;
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hResMode : std_logic_vector(2 downto 0);
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end record;
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end package; |