mirror of
https://github.com/MiSTer-devel/PSX_MiSTer.git
synced 2026-04-19 03:04:52 +00:00
372a534e8d
- GPU: restructure most GPU modules to complete VRAM request even when core is paused - GPU: don't reread fetched vram data after unpausing - Digital pad can now use left Analog Stick as virtual DPad - SNAC input pins clocked in twice to prevent metastability
391 lines
16 KiB
VHDL
391 lines
16 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library mem;
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entity gpu_rect is
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port
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(
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clk2x : in std_logic;
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clk2xIndex : in std_logic;
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ce : in std_logic;
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reset : in std_logic;
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REPRODUCIBLEGPUTIMING: in std_logic;
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error : out std_logic;
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DrawPixelsMask : in std_logic;
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interlacedDrawing : in std_logic;
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activeLineLSB : in std_logic;
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drawingOffsetX : in signed(10 downto 0);
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drawingOffsetY : in signed(10 downto 0);
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drawingAreaLeft : in unsigned(9 downto 0);
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drawingAreaRight : in unsigned(9 downto 0);
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drawingAreaTop : in unsigned(8 downto 0);
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drawingAreaBottom : in unsigned(8 downto 0);
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fifoOut_idle : in std_logic;
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pipeline_busy : in std_logic;
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pipeline_stall : in std_logic;
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pipeline_new : out std_logic := '0';
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pipeline_texture : out std_logic := '0';
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pipeline_transparent : out std_logic := '0';
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pipeline_rawTexture : out std_logic := '0';
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pipeline_x : out unsigned(9 downto 0) := (others => '0');
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pipeline_y : out unsigned(8 downto 0) := (others => '0');
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pipeline_cr : out unsigned(7 downto 0) := (others => '0');
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pipeline_cg : out unsigned(7 downto 0) := (others => '0');
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pipeline_cb : out unsigned(7 downto 0) := (others => '0');
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pipeline_u : out unsigned(7 downto 0) := (others => '0');
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pipeline_v : out unsigned(7 downto 0) := (others => '0');
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proc_idle : in std_logic;
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fifo_Valid : in std_logic;
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fifo_data : in std_logic_vector(31 downto 0);
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requestFifo : out std_logic := '0';
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done : out std_logic := '0';
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CmdDone : out std_logic := '0';
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requestVRAMEnable : out std_logic;
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requestVRAMXPos : out unsigned(9 downto 0);
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requestVRAMYPos : out unsigned(8 downto 0);
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requestVRAMSize : out unsigned(10 downto 0);
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requestVRAMIdle : in std_logic;
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requestVRAMDone : in std_logic;
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textPalNew : out std_logic := '0';
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textPalX : out unsigned(9 downto 0) := (others => '0');
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textPalY : out unsigned(8 downto 0) := (others => '0');
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vramLineEna : out std_logic;
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vramLineAddr : out unsigned(9 downto 0)
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);
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end entity;
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architecture arch of gpu_rect is
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type tState is
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(
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IDLE,
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REQUESTPOS,
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REQUESTTEXTURE,
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REQUESTSIZE,
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CHECKPOS,
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REQUESTFIRST,
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REQUESTLINE,
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READWAIT,
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PROCPIXELS,
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WAITIMING
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);
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signal state : tState := IDLE;
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signal drawTiming : unsigned(31 downto 0);
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signal targetTiming : unsigned(31 downto 0);
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signal rec_texture : std_logic := '0';
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signal rec_size : std_logic_vector(1 downto 0) := "00";
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signal rec_transparency : std_logic := '0';
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signal rec_rawTexture : std_logic := '0';
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signal rec_color : std_logic_vector(23 downto 0) := (others => '0');
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signal rec_posx : signed(11 downto 0) := (others => '0');
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signal rec_sizex : unsigned(9 downto 0) := (others => '0');
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signal rec_sizey : unsigned(8 downto 0) := (others => '0');
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signal rec_u : unsigned(7 downto 0) := (others => '0');
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signal xPos : signed(11 downto 0) := (others => '0');
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signal yPos : signed(11 downto 0) := (others => '0');
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signal xCnt : unsigned(9 downto 0) := (others => '0');
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signal yCnt : unsigned(8 downto 0) := (others => '0');
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signal uWork : unsigned(7 downto 0) := (others => '0');
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signal vWork : unsigned(7 downto 0) := (others => '0');
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signal firstPixel : std_logic;
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signal timeout : integer range 0 to 1048575 := 0;
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begin
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requestFifo <= '1' when (state = REQUESTPOS or state = REQUESTTEXTURE or state = REQUESTSIZE) else '0';
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requestVRAMEnable <= '1' when (state = REQUESTLINE and requestVRAMIdle = '1' and pipeline_stall = '0') else '0';
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requestVRAMXPos <= unsigned(xPos(9 downto 0)) when (state = REQUESTLINE and requestVRAMIdle = '1' and pipeline_stall = '0') else (others => '0');
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requestVRAMYPos <= unsigned(yPos(8 downto 0)) when (state = REQUESTLINE and requestVRAMIdle = '1' and pipeline_stall = '0') else (others => '0');
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requestVRAMSize <= '0' & rec_sizex when (state = REQUESTLINE and requestVRAMIdle = '1' and pipeline_stall = '0') else (others => '0');
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vramLineEna <= '1' when (state = PROCPIXELS) else '0';
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vramLineAddr <= unsigned(xPos(9 downto 0)) when (state = PROCPIXELS) else (others => '0');
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process (clk2x)
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variable xrec12 : signed(11 downto 0);
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variable yrec12 : signed(11 downto 0);
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variable xsize : signed(11 downto 0);
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variable ysize : signed(11 downto 0);
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variable xdiff : signed(11 downto 0);
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variable ydiff : signed(11 downto 0);
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variable ynew : signed(11 downto 0);
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variable yAdd : integer range 1 to 2;
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begin
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if rising_edge(clk2x) then
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-- must be done here, so it also is effected when ce is off = paused
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if (state = READWAIT) then
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if (requestVRAMDone = '1') then
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state <= PROCPIXELS;
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end if;
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end if;
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if (reset = '1') then
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state <= IDLE;
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elsif (ce = '1') then
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done <= '0';
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CmdDone <= '0';
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pipeline_new <= '0';
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pipeline_texture <= '0';
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pipeline_transparent <= '0';
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pipeline_rawTexture <= '0';
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pipeline_x <= (others => '0');
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pipeline_y <= (others => '0');
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pipeline_cr <= (others => '0');
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pipeline_cg <= (others => '0');
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pipeline_cb <= (others => '0');
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pipeline_u <= (others => '0');
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pipeline_v <= (others => '0');
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textPalNew <= '0';
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textPalX <= (others => '0');
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textPalY <= (others => '0');
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if (state /= IDLE) then
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drawTiming <= drawTiming + 1;
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end if;
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error <= '0';
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if (state = IDLE) then
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timeout <= 0;
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elsif (timeout < 1048575) then
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timeout <= timeout + 1;
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else
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error <= '1';
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state <= IDLE;
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done <= '1';
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end if;
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case (state) is
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when IDLE =>
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drawTiming <= (others => '0');
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firstPixel <= '1';
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if (proc_idle = '1' and fifo_Valid = '1' and fifo_data(31 downto 29) = "011") then
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state <= REQUESTPOS;
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rec_texture <= fifo_data(26);
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rec_size <= fifo_data(28 downto 27);
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rec_transparency <= fifo_data(25);
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rec_rawTexture <= fifo_data(24);
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rec_color <= fifo_data(23 downto 0);
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end if;
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when REQUESTPOS =>
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xCnt <= (others => '0');
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yCnt <= (others => '0');
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case (rec_size) is
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when "01" =>
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rec_sizex <= to_unsigned(1, 10);
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rec_sizey <= to_unsigned(1, 9);
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when "10" =>
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rec_sizex <= to_unsigned(8, 10);
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rec_sizey <= to_unsigned(8, 9);
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when "11" =>
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rec_sizex <= to_unsigned(16, 10);
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rec_sizey <= to_unsigned(16, 9);
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when others => null;
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end case;
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if (fifo_Valid = '1') then
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xrec12 := resize(drawingOffsetX, 12) + signed('0' & fifo_data(10 downto 0));
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yrec12 := resize(drawingOffsetY, 12) + signed('0' & fifo_data(26 downto 16));
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rec_posx <= resize(xrec12(10 downto 0), 12);
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yPos <= resize(yrec12(10 downto 0), 12);
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if (rec_texture = '1') then
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state <= REQUESTTEXTURE;
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elsif (rec_size = "00") then
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state <= REQUESTSIZE;
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else
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state <= CHECKPOS;
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CmdDone <= '1';
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end if;
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end if;
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when REQUESTTEXTURE =>
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if (fifo_Valid = '1') then
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uWork <= unsigned(fifo_data( 7 downto 0));
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vWork <= unsigned(fifo_data(15 downto 8));
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rec_u <= unsigned(fifo_data( 7 downto 0));
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textPalX <= unsigned(fifo_data(21 downto 16)) & "0000";
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textPalY <= unsigned(fifo_data(30 downto 22));
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textPalNew <= '1';
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if (rec_size = "00") then
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state <= REQUESTSIZE;
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else
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state <= CHECKPOS;
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CmdDone <= '1';
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end if;
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end if;
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when REQUESTSIZE =>
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if (fifo_Valid = '1') then
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rec_sizex <= unsigned(fifo_data(9 downto 0));
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rec_sizey <= unsigned(fifo_data(24 downto 16));
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state <= CHECKPOS;
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CmdDone <= '1';
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end if;
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when CHECKPOS =>
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if (rec_transparency = '1' or rec_texture = '1') then
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targetTiming <= to_unsigned(50 + to_integer(rec_sizex * rec_sizey * to_unsigned(4, 4)), 32);
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else
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targetTiming <= to_unsigned(50 + to_integer(rec_sizex * rec_sizey * to_unsigned(2, 4)), 32);
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end if;
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xsize := to_signed(to_integer(rec_sizex), 12);
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xdiff := (others => '0');
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if (rec_posx < to_integer(drawingAreaLeft)) then
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xdiff := to_signed(to_integer(drawingAreaLeft), 12) - rec_posx;
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xsize := xsize - xdiff;
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end if;
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rec_posx <= rec_posx + xdiff;
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xPos <= rec_posx + xdiff;
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uWork <= uWork + unsigned(xdiff(7 downto 0));
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rec_u <= rec_u + unsigned(xdiff(7 downto 0));
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rec_sizex <= unsigned(xsize(9 downto 0));
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ysize := to_signed(to_integer(rec_sizey), 12);
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ydiff := (others => '0');
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if (to_integer(yPos) < to_integer(drawingAreaTop)) then
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ydiff := to_signed(to_integer(drawingAreaTop), 12) - yPos;
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ysize := ysize - ydiff;
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end if;
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ynew := yPos + ydiff;
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if (interlacedDrawing = '1' and (activeLineLSB = ynew(0))) then
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ydiff := ydiff + 1;
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ysize := ysize - 1;
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end if;
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yPos <= yPos + ydiff;
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vWork <= vWork + unsigned(ydiff(7 downto 0));
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rec_sizey <= unsigned(ysize(8 downto 0));
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if (xsize < 1 or ysize < 1 or rec_posx > to_integer(drawingAreaRight) or yPos > to_integer(drawingAreaBottom)) then
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if (REPRODUCIBLEGPUTIMING = '1') then
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state <= WAITIMING;
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else
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state <= IDLE;
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done <= '1';
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end if;
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elsif (rec_transparency = '1' or DrawPixelsMask = '1') then
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state <= REQUESTFIRST;
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else
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state <= PROCPIXELS;
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end if;
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when REQUESTFIRST =>
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if (pipeline_busy = '0' and fifoOut_idle = '1') then
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state <= REQUESTLINE;
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end if;
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when REQUESTLINE =>
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if (pipeline_stall = '0' and requestVRAMIdle = '1') then
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state <= READWAIT;
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end if;
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when READWAIT => null; -- handled outside due to ce
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when PROCPIXELS =>
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if (pipeline_stall = '0' and (firstPixel = '0' or pipeline_busy = '0')) then
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firstPixel <= '0';
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xCnt <= xCnt + 1;
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xPos <= xPos + 1;
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uWork <= uWork + 1;
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if (xCnt + 1 >= rec_sizex or xPos + 1 > to_integer(drawingAreaRight)) then
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yAdd := 1;
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if (interlacedDrawing = '1') then
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yAdd := 2;
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end if;
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yCnt <= yCnt + yAdd;
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ypos <= yPos + yAdd;
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vWork <= vWork + yAdd;
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if (yCnt + yAdd >= rec_sizey or ypos + yAdd > to_integer(drawingAreaBottom)) then
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if (REPRODUCIBLEGPUTIMING = '1') then
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state <= WAITIMING;
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else
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state <= IDLE;
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done <= '1';
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end if;
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else
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xPos <= rec_posx;
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xCnt <= (others => '0');
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uWork <= rec_u;
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if (rec_transparency = '1' or DrawPixelsMask = '1') then
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state <= REQUESTLINE;
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end if;
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end if;
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end if;
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if (xPos >= to_integer(drawingAreaLeft) and xPos <= to_integer(drawingAreaRight) and ypos >= to_integer(drawingAreaTop) and ypos <= to_integer(drawingAreaBottom)) then
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pipeline_new <= '1';
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pipeline_texture <= rec_texture;
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pipeline_transparent <= rec_transparency;
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pipeline_rawTexture <= rec_rawTexture;
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pipeline_x <= unsigned(xPos(9 downto 0));
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pipeline_y <= unsigned(yPos(8 downto 0));
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pipeline_cr <= unsigned(rec_color( 7 downto 0));
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pipeline_cg <= unsigned(rec_color(15 downto 8));
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pipeline_cb <= unsigned(rec_color(23 downto 16));
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pipeline_u <= uWork;
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pipeline_v <= vWork;
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end if;
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end if;
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if (drawingAreaLeft > drawingAreaRight or drawingAreaTop > drawingAreaBottom) then
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if (REPRODUCIBLEGPUTIMING = '1') then
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state <= WAITIMING;
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else
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state <= IDLE;
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done <= '1';
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end if;
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end if;
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when WAITIMING =>
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if (clk2xIndex = '0' and drawTiming + 4 >= targetTiming) then
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state <= IDLE;
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done <= '1';
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end if;
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end case;
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end if;
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end if;
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end process;
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end architecture;
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