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119 lines
4.5 KiB
VHDL
119 lines
4.5 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity gpu_dither is
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generic
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(
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img_width : integer := 1024;
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color_width : integer := 8;
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reduced_width : integer := 6
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);
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port
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(
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clk : in std_logic;
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ce : in std_logic;
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x : in integer range 0 to img_width-1;
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firstLine : in std_logic;
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din_r : in std_logic_vector(color_width-1 downto 0);
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din_g : in std_logic_vector(color_width-1 downto 0);
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din_b : in std_logic_vector(color_width-1 downto 0);
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dout_r : out std_logic_vector(color_width-1 downto 0) := (others => '0');
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dout_g : out std_logic_vector(color_width-1 downto 0) := (others => '0');
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dout_b : out std_logic_vector(color_width-1 downto 0) := (others => '0')
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);
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end entity;
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architecture arch of gpu_dither is
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constant dither_bits : integer := color_width - reduced_width;
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constant dither_bits1 : integer := dither_bits + 1;
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type t_dither_rgb is array(1 to 3) of unsigned(dither_bits-1 downto 0);
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signal dither_buffer_next : t_dither_rgb := (others => (others =>'0'));
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signal dither_buffer_newline : t_dither_rgb := (others => (others =>'0'));
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type t_dither_rgb1 is array(1 to 3) of std_logic_vector(dither_bits1-1 downto 0);
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signal dither_buffer_toRam : t_dither_rgb1 := (others => (others =>'0'));
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signal dither_buffer_fromRam : t_dither_rgb1 := (others => (others =>'0'));
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signal index : integer range 0 to img_width-1 := 0;
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signal AddrA : integer range 0 to img_width-1 := 0;
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signal WEA : std_logic := '0';
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signal dataB : std_logic_vector((dither_bits1*3) - 1 downto 0);
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begin
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ilineram: entity work.dpram
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generic map ( addr_width => 10, data_width => dither_bits1 * 3)
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port map
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(
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clock_a => clk,
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address_a => std_logic_vector(to_unsigned(AddrA, 10)),
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data_a => dither_buffer_toRam(1) & dither_buffer_toRam(2) & dither_buffer_toRam(3),
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wren_a => WEA,
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clock_b => clk,
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address_b => std_logic_vector(to_unsigned(x, 10)),
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data_b => ((dither_bits1 * 3) - 1 downto 0 => '0'),
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wren_b => '0',
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q_b => dataB
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);
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dither_buffer_fromRam(1) <= dataB((dither_bits1 * 3)-1 downto (dither_bits1 * 2));
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dither_buffer_fromRam(2) <= dataB((dither_bits1 * 2)-1 downto dither_bits1);
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dither_buffer_fromRam(3) <= dataB(dither_bits1-1 downto 0);
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process (clk)
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type t_intermediate is array(1 to 3) of unsigned(color_width downto 0);
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variable intermediate_color : t_intermediate;
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begin
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if rising_edge(clk) then
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WEA <= '0';
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if (ce = '1') then
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intermediate_color(1) := ("0" & unsigned(din_r));
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intermediate_color(2) := ("0" & unsigned(din_g));
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intermediate_color(3) := ("0" & unsigned(din_b));
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if (x > 0) then
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intermediate_color(1) := intermediate_color(1) + dither_buffer_next(1);
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intermediate_color(2) := intermediate_color(2) + dither_buffer_next(2);
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intermediate_color(3) := intermediate_color(3) + dither_buffer_next(3);
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end if;
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if (firstLine = '0') then
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intermediate_color(1) := intermediate_color(1) + unsigned(dither_buffer_fromRam(1));
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intermediate_color(2) := intermediate_color(2) + unsigned(dither_buffer_fromRam(2));
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intermediate_color(3) := intermediate_color(3) + unsigned(dither_buffer_fromRam(3));
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end if;
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for c in 1 to 3 loop
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if (intermediate_color(c)(8) = '1') then intermediate_color(c) := '0' & to_unsigned((2**color_width) - 1, color_width); end if;
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dither_buffer_next(c) <= "0" & intermediate_color(c)(dither_bits-2 downto 0);
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dither_buffer_newline(c) <= intermediate_color(c)(dither_bits-1 downto 0);
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dither_buffer_toRam(c) <= std_logic_vector(('0' & intermediate_color(c)(dither_bits-1 downto 0)) + dither_buffer_newline(c));
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end loop;
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index <= x;
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AddrA <= index;
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WEA <= '1';
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dout_r <= std_logic_vector(intermediate_color(1)(color_width-1 downto 0));
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dout_g <= std_logic_vector(intermediate_color(2)(color_width-1 downto 0));
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dout_b <= std_logic_vector(intermediate_color(3)(color_width-1 downto 0));
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end if;
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end if;
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end process;
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end architecture; |