mirror of
https://github.com/MiSTer-devel/PSX_MiSTer.git
synced 2026-05-17 03:04:24 +00:00
4569b1ba6f
- GPU: rework Palette cache reset(fixes Castrol Honda Superbike Racing flickering content) - GPU: more robust 24 Bit Fifo handling
270 lines
9.8 KiB
VHDL
270 lines
9.8 KiB
VHDL
-----------------------------------------------------------------
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--------------- Export Package --------------------------------
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-----------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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package pexport is
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type tExportRegs is array(0 to 31) of unsigned(31 downto 0);
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signal regs : tExportRegs;
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type cpu_export_type is record
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regs : tExportRegs;
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pc : unsigned(31 downto 0);
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opcode : unsigned(31 downto 0);
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cause : unsigned(31 downto 0);
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end record;
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end package;
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-----------------------------------------------------------------
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--------------- Export module --------------------------------
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-----------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use STD.textio.all;
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use work.pexport.all;
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entity export is
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generic
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(
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export_index : std_logic := '1';
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export_time : std_logic := '0'
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);
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port
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(
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clk : in std_logic;
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ce : in std_logic;
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reset : in std_logic;
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new_export : in std_logic;
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export_cpu : in cpu_export_type;
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export_irq : in unsigned(15 downto 0);
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export_gtm : in unsigned(11 downto 0);
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export_line : in unsigned(11 downto 0);
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export_gpus : in unsigned(31 downto 0);
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export_gobj : in unsigned(15 downto 0);
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export_t_current0 : in unsigned(15 downto 0);
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export_t_current1 : in unsigned(15 downto 0);
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export_t_current2 : in unsigned(15 downto 0);
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export_8 : in std_logic_vector(7 downto 0);
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export_16 : in std_logic_vector(15 downto 0);
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export_32 : in std_logic_vector(31 downto 0)
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);
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end entity;
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architecture arch of export is
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signal newticks : unsigned(11 downto 0) := (others => '0');
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signal totalticks : unsigned(31 downto 0) := (others => '0');
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signal cyclenr : unsigned(31 downto 0) := x"00000001";
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signal reset_1 : std_logic := '0';
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signal export_reset : std_logic := '0';
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signal exportnow : std_logic;
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signal export_cpu_last : cpu_export_type := ((others => (others => '0')), (others => '0'), (others => '0'), (others => '0'));
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signal export_irq_last : unsigned(15 downto 0) := (others => '0');
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signal export_gtm_last : unsigned(11 downto 0) := (others => '0');
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signal export_line_last : unsigned(11 downto 0) := (others => '0');
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signal export_gpus_last : unsigned(31 downto 0) := (others => '0');
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signal export_gobj_last : unsigned(15 downto 0) := (others => '0');
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signal export_t_current0_last : unsigned(15 downto 0) := (others => '0');
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signal export_t_current1_last : unsigned(15 downto 0) := (others => '0');
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signal export_t_current2_last : unsigned(15 downto 0) := (others => '0');
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function to_lower(c: character) return character is
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variable l: character;
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begin
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case c is
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when 'A' => l := 'a';
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when 'B' => l := 'b';
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when 'C' => l := 'c';
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when 'D' => l := 'd';
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when 'E' => l := 'e';
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when 'F' => l := 'f';
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when 'G' => l := 'g';
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when 'H' => l := 'h';
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when 'I' => l := 'i';
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when 'J' => l := 'j';
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when 'K' => l := 'k';
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when 'L' => l := 'l';
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when 'M' => l := 'm';
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when 'N' => l := 'n';
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when 'O' => l := 'o';
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when 'P' => l := 'p';
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when 'Q' => l := 'q';
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when 'R' => l := 'r';
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when 'S' => l := 's';
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when 'T' => l := 't';
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when 'U' => l := 'u';
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when 'V' => l := 'v';
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when 'W' => l := 'w';
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when 'X' => l := 'x';
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when 'Y' => l := 'y';
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when 'Z' => l := 'z';
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when others => l := c;
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end case;
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return l;
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end to_lower;
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function to_lower(s: string) return string is
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variable lowercase: string (s'range);
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begin
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for i in s'range loop
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lowercase(i):= to_lower(s(i));
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end loop;
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return lowercase;
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end to_lower;
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begin
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-- synthesis translate_off
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process(clk)
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begin
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if rising_edge(clk) then
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if (reset = '1') then
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totalticks <= (others => '0');
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newticks <= (others => '0');
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elsif (ce = '1') then
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totalticks <= totalticks + 1;
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newticks <= newticks + 1;
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if (exportnow = '1') then
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newticks <= x"001";
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end if;
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end if;
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reset_1 <= reset;
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end if;
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end process;
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export_reset <= '1' when (reset = '0' and reset_1 = '1') else '0';
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exportnow <= new_export;
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process
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file outfile: text;
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file outfile_irp: text;
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variable f_status: FILE_OPEN_STATUS;
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variable line_out : line;
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variable recordcount : integer := 0;
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constant filenamebase : string := "R:\\debug_sim";
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variable filename_current : string(1 to 25);
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begin
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filename_current := filenamebase & "00000000.txt";
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file_open(f_status, outfile, filename_current, write_mode);
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file_close(outfile);
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file_open(f_status, outfile, filename_current, append_mode);
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while (true) loop
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wait until rising_edge(clk);
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if (reset = '1') then
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cyclenr <= x"00000001";
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filename_current := filenamebase & "00000000.txt";
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file_close(outfile);
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file_open(f_status, outfile, filename_current, write_mode);
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file_close(outfile);
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file_open(f_status, outfile, filename_current, append_mode);
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end if;
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if (exportnow = '1') then
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if (export_index = '1') then
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write(line_out, string'("# "));
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write(line_out, to_lower(to_hstring(cyclenr - 1)) & " ");
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end if;
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if (export_time = '1') then
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write(line_out, string'("# "));
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write(line_out, to_lower(to_hstring(totalticks - 1)) & " ");
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write(line_out, string'("# "));
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write(line_out, to_lower(to_hstring(newticks)) & " ");
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end if;
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write(line_out, string'("PC "));
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write(line_out, to_lower(to_hstring(export_cpu.pc)) & " ");
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write(line_out, string'("OP "));
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write(line_out, to_lower(to_hstring(export_cpu.opcode)) & " ");
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for i in 0 to 31 loop
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if (export_cpu.regs(i) /= export_cpu_last.regs(i)) then
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write(line_out, string'("R"));
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if (i < 10) then
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write(line_out, string'("0"));
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end if;
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write(line_out, to_lower(to_string(i)));
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write(line_out, string'(" "));
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write(line_out, to_lower(to_hstring(export_cpu.regs(i))) & " ");
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end if;
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end loop;
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if (export_cpu.cause /= export_cpu_last.cause) then write(line_out, string'("CAUSE ")); write(line_out, to_lower(to_hstring(export_cpu.cause)) & " "); end if;
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if (export_irq /= export_irq_last) then write(line_out, string'("IRQ ")); write(line_out, to_lower(to_hstring(export_irq)) & " "); end if;
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if (export_time = '1') then
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if (export_gtm /= export_gtm_last) then write(line_out, string'("GTM ")); write(line_out, to_lower(to_hstring(export_gtm)) & " "); end if;
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if (export_line /= export_line_last) then write(line_out, string'("LINE ")); write(line_out, to_lower(to_hstring(export_line)) & " "); end if;
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if (export_gpus /= export_gpus_last) then write(line_out, string'("GPUS ")); write(line_out, to_lower(to_hstring(export_gpus)) & " "); end if;
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if (export_gobj /= export_gobj_last) then write(line_out, string'("GOBJ ")); write(line_out, to_lower(to_hstring(export_gobj)) & " "); end if;
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if (export_t_current0 /= export_t_current0_last) then write(line_out, string'("T0 ")); write(line_out, to_lower(to_hstring(export_t_current0)) & " "); end if;
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if (export_t_current1 /= export_t_current1_last) then write(line_out, string'("T1 ")); write(line_out, to_lower(to_hstring(export_t_current1)) & " "); end if;
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if (export_t_current2 /= export_t_current2_last) then write(line_out, string'("T2 ")); write(line_out, to_lower(to_hstring(export_t_current2)) & " "); end if;
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end if;
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writeline(outfile, line_out);
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cyclenr <= cyclenr + 1;
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if (cyclenr mod 10000000 = 0) then
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filename_current := filenamebase & to_hstring(cyclenr) & ".txt";
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file_close(outfile);
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file_open(f_status, outfile, filename_current, write_mode);
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file_close(outfile);
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file_open(f_status, outfile, filename_current, append_mode);
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end if;
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export_cpu_last <= export_cpu;
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export_irq_last <= export_irq;
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export_gtm_last <= export_gtm;
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export_line_last <= export_line;
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export_gpus_last <= export_gpus;
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export_gobj_last <= export_gobj;
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export_t_current0_last <= export_t_current0;
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export_t_current1_last <= export_t_current1;
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export_t_current2_last <= export_t_current2;
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end if;
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end loop;
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end process;
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-- synthesis translate_on
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end architecture;
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