81 Commits

Author SHA1 Message Date
Brendan Saricks
f969793882 Kuba's fixes from Main (#347)
* Release 20251204

* Update sys

* Implement real Mechacon backward-seek behavior (skip only when ≥2 sectors behind)

Fix for Dave Mirra / Trasher games
https://github.com/MiSTer-devel/PSX_MiSTer/issues/169

* keep track of savestate slot status and allow load only for valid states/slots

* Add optional Backward Seek Hack (OSD toggle) - fix Dave Mirra/Thrasher games

Fix for Dave Mirra/Thrasher is generally safe for most titles (tested over 200+ games ), but known to cause issues in some Army Men games.
It must be some edge case that cannot tolerate this change. Anyway, the problem with Dave Mirra is also like that :)

Kept as an unsafe optional setting until a proper fix is available. This is the best solution for now, and it would be a shame to lose the opportunity to comfortably play Dave Mirra and Trasher games

* Add optional Backward Seek Hack (OSD toggle) - fix Dave Mirra/Thrasher games

Fix for Dave Mirra/Thrasher is generally safe for most titles (tested over 200+ games ), but known to cause issues in some Army Men games.
It must be some edge case that cannot tolerate this change. Anyway, the problem with Dave Mirra is also like that :)

Kept as an unsafe optional setting until a proper fix is available. This is the best solution for now, and it would be a shame to lose the opportunity to comfortably play Dave Mirra and Trasher games

* Update README.md

* Update PSX.sv

* CD: Fix INT1 handling

CD: Fix INT1 vs INT3 interrupt ordering

Some games rely on very strict CDROM interrupt ordering and timing:
Gokujou Parodius Da! Deluxe Pack and Crime Crackers require INT1 to be visible immediately after a sector becomes readable.
Jikkyō Powerful Pro Yakyū ’95 relies on INT3 responses being fully processed before INT1, otherwise FIFO responses are read in the wrong order, causing music stutter.

This change refines INT1 delivery logic.
INT1 is forced immediately when no conflicting INT3 is active (required by Parodius / Crime Crackers).
INT1 is deferred (queued) when INT3 is currently active, preventing response/FIFO ordering issues (required by Jikkyō ’95).
Any active non-INT1 IRQ is preserved using the existing pendingDriveIRQ mechanism.

* Update PSX.sv

* Update README.md

* CD: fix DMA read from empty sector buffer

- The previous code could start a CD-ROM DMA transfer even when sectorBufferSizes(readPtr) was zero, and it cleared the buffer size flag before copySize was latched, leading to reads from empty buffers and propagation of invalid data.

- The new logic only starts DMA when a valid sector is present and latches the sector size before clearing the ready flag, eliminating the race condition.

* CD: Fix PAUSE timing to match psx-spx and DuckStation

* CD: prevent DMA from empty sector buffers while allowing RAW reads

fixes some regressions (Gran Turismo 2)

* rework INT1 handling

fix regression Burger Burger

* add cpu exception breakpoint functionality

* CD: correct PAUSE behavior during seek and early read states (fix Parasite Eve II)

Parasite Eve II issues a PAUSE command while a seek is still in progress and expects the pending read to be cancelled.
The previous logic rejected PAUSE too broadly, causing the read to execute after the seek and hang the loading screen.
This change accepts PAUSE during SEEK and stops the pending read, restoring correct PE2 behavior.

* reverting changes for “pause swap”

* CD: Correct Pause handling during SEEK

fix Vigilante 8: 2nd Offense black screen 
https://github.com/MiSTer-devel/PSX_MiSTer/issues/296

* unnecessary backward seek hack removed

The issue wasn't caused by backward seek itself, but by interrupt ordering.
There was a race condition between INT1 (Data Ready) and INT3. 
Fixed with commit be26ea591e

* unnecessary backward seek hack removed

The issue wasn't caused by backward seek itself, but by interrupt ordering.
There was a race condition between INT1 (Data Ready) and INT3. 
Fixed with commit be26ea591e

* unnecessary backward seek hack removed

The issue wasn't caused by backward seek itself, but by interrupt ordering.
There was a race condition between INT1 (Data Ready) and INT3. 
Fixed with commit be26ea591e

* Update README.md

unnecessary backward seek hack removed

* unused warning bit removed

* Update README.md

* Update sys_top.sdc

* Delete PSX_20251204.rbf

* Revert "Update sys_top.sdc"

This reverts commit 2058c5ef45.

---------

Co-authored-by: RobertPeip <53250236+RobertPeip@users.noreply.github.com>
Co-authored-by: jackyangantelope <jack@retroremake.co>
Co-authored-by: kuba-j <jhajda@poczta.fm>
Co-authored-by: Robert <->
Co-authored-by: dtungsten <github@draketungsten.net>
2026-02-28 17:20:32 +01:00
Robert Peip
c90496401c fixed a bug that could lead to wrong values being cached when using Turbo(fixed a crash when using Turbo in e.g. Chrono Cross) 2022-12-09 16:57:47 +01:00
Robert Peip
38552ccf76 - SPU: repeat ignore also when voice is off(fixes repeated voices in Alien Resurrection)
- SPU: add debug feature to trigger a SPU IRQ
- Preliminary change for black screen on screen transition. Might change in future commits, as it's framework related
2022-12-04 19:28:42 +01:00
Robert Peip
4569b1ba6f - Video: set interlace field when turning on interlaced mode based on odd/even frame(fixes Next Tetris hang)
- GPU: rework Palette cache reset(fixes Castrol Honda Superbike Racing flickering content)
- GPU: more robust 24 Bit Fifo handling
2022-11-17 16:33:01 +01:00
Robert Peip
22d94a76d2 - GPU: GPUSTAT_DrawingOddline on/off moved slightly before line end in 240p mode -> fulfills test against hardware
- GPU: GPUSTAT_DrawingOddline on moved one line earlier in 480i mode -> fulfills test against hardware
- disable automatic reset when switching CDs while LID is open in OSD
2022-11-16 09:19:50 +01:00
Robert Peip
fb7e47134d GPU: fix timing of GPUSTAT bits odd-even(31) and interlace field(13) around vsync 2022-11-14 18:33:26 +01:00
Robert Peip
22042e9ca6 add 480i to 480p hack 2022-10-27 18:48:46 +02:00
Robert Peip
594c30c39a - DMA: implement configurable CD timing(memctrl)
- DMA: corrected block mode pausing
- DMA: corrected linked list mode starting pause, and timing between list entries
- DMA: simplified linked list mode data reading and autoread logic
2022-10-24 17:58:30 +02:00
Robert Peip
1ab11e32e3 - DMA: allow to read DMA over full page instead of 4 word boundary (average 1.5 cycles less overhead -> matching PSX test)
- SDRAM: change 8 word burst to 4*2 word bursts to allow for unwrapped page reads for DMA
- restructure savestates for memctrl, dma, timer and sio (resource reduction)
- fix cheats being turning off when turbo is on
2022-10-21 17:41:31 +02:00
Robert Peip
37c6c3a6ca - DMA: allow for early DMA stop when last word is transferred from ram to device -> 2 cycles less DMA overhead
- DMA: moved IRQ to trigger 1 cycle earlier
- removed DMAinBLOCKs option
- moved OSD Overlay option to Misc
2022-10-16 09:15:30 +02:00
Robert Peip
b7ea48bd45 - implement 24bit rendering
- add 8mbyte ram option
2022-10-12 14:07:56 +02:00
Robert Peip
675a7be76e - exchanged "unreal" texture filter with bilinear texture filter
- add options to only filter dithered or shaded polygons
- add option to detect pure 2D polygons with a heuristic and skip filtering those
2022-10-05 10:59:47 +02:00
Robert Peip
118bd85644 - corrected uncached instruction fetch timing
- corrected bios instruction fetch timing
- implement partial cache line fetch for BIOS
2022-09-26 18:16:23 +02:00
Robert Peip
8b06b2656e implement 3 different turbo speeds:
- Low: slightly faster ram access
- Medium: additionally 50% cache hit rate
- High: full cache hit rate + speedups for DMA, GTE and CPU
2022-09-24 16:39:58 +02:00
Robert Peip
7bb471d59b - DMA: early stop ram autoread as soon as all required data is requested
- DMA: add separate state for DMA start and reduce start intitial overhead by 2 cycles
- RAM: ram reqprocessed only used for dma now -> removes risk of CPU reads influencing DMA reads
- Savestates: fix reset when loading .exe files
2022-09-24 13:42:48 +02:00
Robert Peip
1ed4583a44 - DMA/RAM: remove 128bit data bus, deliver data to DMA with every 32bit word -> lower ressource usage and lower latency
- DMA: due to seperate ram ready signals for DMA, DMA does not have to wait for pending data before switching back to CPU -> lower latency when DMA ends
- DMA: unify blocklength calculation for DMA to/from SDRAM
- Savestates: wait for valid spot before going into reset/savestate load
- Savestates: add retry logic if reset ends in permanten pausing or permanent not pausible situation
2022-09-23 18:25:19 +02:00
Robert Peip
35fc3b653f - Savestates: wait until HPS is no longer busy before unpausing after taking a savestate
- Memory: don't access savestate data as cpu cache -> fixes random bugs after taking a savestate(bug introduced with last build)
- Memory: unify data rotation for data from ram and bios
- exe loading: store header values at .exe download instead of fetching them from sdram later
2022-09-21 16:23:34 +02:00
Robert Peip
47015db0f1 - rework sdram -> instruction cache interface, reducing cache fetch time by 1 cycle, fulfilling test against hardware
- fix savestate slot index when reloading core
2022-09-19 17:30:05 +02:00
Robert Peip
a464a734ec - CPU: make instruction fetch stage fully independent of data fetch stage
- CPU: simplify and clean up instruction fetch stage
- some simulation fixes
2022-09-11 15:34:39 +02:00
Robert Peip
1204671b68 Simulation: added asymmetric dpram simulation model and remove all altera primitives from simulation 2022-09-10 13:39:39 +02:00
Robert Peip
e57b6e6be3 - DMA: 2 cycles less base line timing for DMAs to ram
- DMA: add timing cost for ram page switch
- DMA: add timing cost for ram refresh
- DMA: Turbo option will ignores all timing costs and delivers fastest DMA performance
2022-09-09 17:52:16 +02:00
Robert Peip
a1d0d49dd4 rework DMA->SDRAM interface:
- double write performance from 32bit/2 cycles to 32Bit/1 cycle
- decrease overhead by 4 cycles
2022-08-15 19:59:57 +02:00
Robert Peip
781a122394 add optional hack to limit CD read speed to capability of the game -> allows to use 8x CD speed in more games without CD read overflow 2022-08-05 19:36:37 +02:00
Robert Peip
2c9fefafe0 - CD: fixed bug with second command writing fifo values while IRQ is still pending(Transformers: fixes hang after FMV )
- CD: increased minimum seek time until better values/model are implemented(Transformers: fixes hang in loading screen)
- option for fixed CD speed added(1X-8X)
- error overlay off by default
2022-08-01 21:06:30 +02:00
Robert Peip
7ddd409943 - CDXA: ignore sector if there is still data in the decode fifo (fixes Rugrats - Search for Reptar)
- Memcard: fix wrong lastData responses
2022-07-29 20:04:47 +02:00
Robert Peip
2cffc9fe8b CPU: fix design flaw that didn't allow to pause CPU for DMA when CPU is constantly doing memory accesses (fixes Rascal Option menu rendering) 2022-07-23 17:49:10 +02:00
Robert Peip
379d85f594 GPU: skip drawing line primitives that are fully outside the drawingArea (fixed FF9 rain slowdown) 2022-07-21 15:23:36 +02:00
Robert Peip
372a534e8d - GPU: allow output of videodata while core is paused(fixes glitches when unpausing)
- GPU: restructure most GPU modules to complete VRAM request even when core is paused
- GPU: don't reread fetched vram data after unpausing
- Digital pad can now use left Analog Stick as virtual DPad
- SNAC input pins clocked in twice to prevent metastability
2022-07-16 12:02:00 +02:00
Robert Peip
e836b28989 - spu irq only for new decoded adpcm, also fixes bug where irq would be generated for first address behind adpcm end address(shadowman, lego islands 2)
- reorder gamepads in OSD
- hide debug menu until L3+R3+Select is pressed
2022-05-03 18:01:14 +02:00
Robert Peip
913b98a8ce - dualshock implementation from markun merged
- some fixes and additions
- Overlay when switching dualshock mode
- manual analog mode switch with either mouseclick or L3+R3+DPad Up/Down
2022-04-27 12:13:32 +02:00
Robert Peip
b385978687 - CPU: don't go in interrupt if already handling exception in same CPU cycle (e.g. Resident Evil)
- Joypad: added ack hold time (fixes Resident Evil controller loss)
- fix widescreen hack wraparound glitches
- add widescreen hack modes for 5:3 and 3:2
- longer savestate wait when saving to sdcard, no wait when not saving
2022-04-08 17:50:01 +02:00
Robert Peip
956a8c4b5d - remove single track CD fetching from HPS
- remove some useless debug options
2022-04-02 16:49:46 +02:00
Robert Peip
4f55ef9a38 - general GPU reset will now also reset processing statemachine and GPU Fifo(fixes E3 hang in Demo 1 Fish-Tech and Racemaster Cheat disk)
- reduce DMA wait time -> more accurate to hardware according to chopping benchmark and fixes NBA transparency
2022-04-01 16:44:59 +02:00
Robert Peip
9c9890df28 - add widescreen hack
- reduce MDEC resource usage(logic -> RAM)
- fix reset of fastboot setting when loading a .exe
- updated sys
2022-03-13 12:58:58 +01:00
Robert Peip
144e77ed3b - add option Sync 480i for HDMI
- SPU gauss table into blockram (ALM reduction)
- MDEC array IDCTtemp into blockram (ALM reduction)
- remove logic for CD loading to SDRAM2
2022-03-12 18:02:33 +01:00
Robert Peip
e61bd8d16d - add experimental data cache (debug options)
- fix savestates for videoout
- CD overlay as option
2022-03-11 19:19:24 +01:00
Robert Peip
8d0a6eab5f - correct aspect ratio down to 128 pixel height(Kitrinx)
- 1 cycle faster CPU -> RAM write (3->2)
- longer DMA pause -> fixes rare PAD issues
2022-03-09 17:47:34 +01:00
Robert Peip
6ca9b78b6f - add video output in pause to prevent sync loss
- shift vsync for PAL
- don't force refresh when going into DMA -> 1 cycle faster DMAs
- decrease DMA setup time by 1 cycle
- skip empty liked list DMAs -> 5 cycles less
2022-03-08 19:01:13 +01:00
Robert Peip
68977d2111 - fix horizontal length exceeding resolution (street fighter alpha 3)
- fix vertical offset for analog out
- improve CPU write time by 1 clock cycle(4->3)
2022-03-07 17:12:19 +01:00
Robert Peip
b05123a032 refactor video out 2022-02-28 15:34:12 +01:00
Robert Peip
15669b03d7 - CPU: fix COP0 registers to not have delays(fixes e.g. FF8, Jumping Flash)
- CPU: block IRQ after after Exceptions(fixes e.g. FF8)
- DMA: writing to D_CHCR does not always request DMA
- DMA: writing to DPCR does not always request DMA
- DMA: manual request works now for all channels
- DMA: don't start and wait with DMA when CPU is in middle of memory access anyway
- DMA resource usage reduced
- added REPtimingGPU for vram2vram
- deactivated gun crosshair because of resource usage
- added "Advance Pause" debug feature: advance 1000 clock cycles in pause mode for each press
2022-02-23 16:22:38 +01:00
Robert Peip
183899295e MDEC: don't clear Fifo when receiving invalid opcodes, so DMA will not send further data (fixes Formula 1 Rev1) 2022-02-20 19:15:24 +01:00
Robert Peip
2d52e62ee1 - CDDA implemented -> still needs Multitrack data read!
- fixed CD(DA/XA) volume init values
- fixed GetTN/GetTD commands
- fixed trackEnd response
- fixed header processing after seek
- fixed readOnDisk on read/play start
- fixed clearSectorBuffer on read/play start
2022-02-16 21:51:50 +01:00
Robert Peip
cd3724191f - fix CD drive response (Syphon Filter hang)
- fix CD fifo reset now stops pending copy (G-Darius FMV hang)
- add better controller options in OSD
- fix some mouse bugs
2022-02-03 18:02:00 +01:00
Robert Peip
2b02a74d8c - first try for SPU RAM in DDR3
- use SPU mute bit
2022-01-22 12:35:45 +01:00
Robert Peip
0744257433 - added SPU interrupts
- full savestate support for sound
- several SPU bugfixes
- add reverb off option to OSD
- updated framework(e.g. new filters)
2022-01-18 20:58:26 +01:00
Robert Peip
f401ac64a7 - add SPU main volume
- add SPU total clamp
- speed up SPU RAM transfer
- errorflag for SPU timeout added (errorcode: EA)
- RAM simulation models for faster simulation
2022-01-15 14:50:30 +01:00
Robert Peip
35e3388f58 first real SPU implementation added 2022-01-14 17:59:32 +01:00
Robert Peip
9ff22725b0 - GPU to DDR3 write throughput doubled
- CPU -> Mem write latency reduced
- implement DisplayDisable
- errorflag for GPU fifo overflow added (E9)
2021-12-22 13:06:53 +01:00
Robert Peip
49b8e285f6 - DMA: 2 cycles instead of 3 cycles per write
- DMA overhead reduced by about 10 clock cycles
- cache fetch 1 cycle faster
- BIOS data/instruction/cache fetch speedup optional(OSD)
- add mask-OR for CPU2VRAM
- errorflags added for CPU2VRAM mask and DMA chopping
2021-12-21 17:00:18 +01:00