mirror of
https://github.com/MiSTer-devel/PMD85_MiSTer.git
synced 2026-05-17 03:04:23 +00:00
2fbfdc7e81
- Upgrade to new MiSTer framework - Added Mega ROM support + one Mega ROM image included - MIF85 clock fix - Keyboard changes to match [PMD85 emulator](https://pmd85.borik.net/wiki/Emulator) from Borik brothers - Added Mouse support - i8253 fix - issue when FFFF value was loaded (Atomix game was missing stripes over logo) - Video output to MiSTer subsystem is now synced with Video Clock (better image fidelity to original HW) - Added PMD85 version 3
58 lines
4.1 KiB
Tcl
58 lines
4.1 KiB
Tcl
#
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#
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derive_pll_clocks
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derive_clock_uncertainty
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# core specific constraints
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# core specific constraints
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#
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#create_generated_clock -name phi1 -source [get_nets {emu|pll|pll_inst|altera_pll_i|outclk_wire[0]}] -divide_by 9 -duty_cycle 22.23 [get_registers {emu:emu|PMD85_core:PMD85_core|i8224:i8224|phi1reg[0]}]
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#create_generated_clock -name phi2 -source [get_nets {emu|pll|pll_inst|altera_pll_i|outclk_wire[0]}] -divide_by 9 -duty_cycle 55.56 [get_registers {emu:emu|PMD85_core:PMD85_core|i8224:i8224|phi2reg[0]}]
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create_generated_clock -name phi1 -source [get_nets {emu|pll|pll_inst|altera_pll_i|outclk_wire[0]}] -divide_by 9 [get_registers {emu:emu|PMD85_core:PMD85_core|i8224:i8224|phi1reg[0]}]
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create_generated_clock -name phi2 -source [get_nets {emu|pll|pll_inst|altera_pll_i|outclk_wire[0]}] -divide_by 9 [get_registers {emu:emu|PMD85_core:PMD85_core|i8224:i8224|phi2reg[0]}]
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#
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#set_multicycle_path -to {emu|PMD85_core|cpu|*} -setup 2
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#set_multicycle_path -to {emu|PMD85_core|cpu|*} -hold 1
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#create_generated_clock -name CAS -source [get_registers {emu:emu|PMD85_2A:PMD85core|i8224:i8224|phi2}] -divide_by 16 -duty_cycle 55.56 [get_registers {emu:emu|PMD85_2A:PMD85core|clk_shift[4]}]
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### SDRAM delays
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#set_input_delay -clock [get_clocks {emu|pll_SDRAM|pll_sdram_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}] -max 6.4 [get_ports SDRAM_DQ[*]]
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#set_input_delay -clock [get_clocks {emu|pll_SDRAM|pll_sdram_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}] -min 3.2 [get_ports SDRAM_DQ[*]]
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#
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#set_output_delay -clock [get_clocks {emu|pll_SDRAM|pll_sdram_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
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#set_output_delay -clock [get_clocks {emu|pll_SDRAM|pll_sdram_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
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#set_output_delay -clock [get_clocks {emu|pll_SDRAM|pll_sdram_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}] -max 1.5 [get_ports {SDRAM_CLK}]
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#set_output_delay -clock [get_clocks {emu|pll_SDRAM|pll_sdram_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}] -min -0.8 [get_ports {SDRAM_CLK}]
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#
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#
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#
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set_input_delay -clock [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -max 6.4 [get_ports SDRAM_DQ[*]]
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set_input_delay -clock [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -min 3.2 [get_ports SDRAM_DQ[*]]
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set_output_delay -clock [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
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set_output_delay -clock [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
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set_output_delay -clock [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -max 1.5 [get_ports {SDRAM_CLK}]
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set_output_delay -clock [get_clocks {emu|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -min -0.8 [get_ports {SDRAM_CLK}]
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#
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#set_input_delay -clock [get_clocks {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -max 6.4 [get_ports SDRAM_DQ[*]]
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#set_input_delay -clock [get_clocks {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -min 3.2 [get_ports SDRAM_DQ[*]]
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#
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#set_output_delay -clock [get_clocks {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
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#set_output_delay -clock [get_clocks {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
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#set_output_delay -clock [get_clocks {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -max 1.5 [get_ports {SDRAM_CLK}]
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#set_output_delay -clock [get_clocks {emu|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -min -0.8 [get_ports {SDRAM_CLK}]
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