Aitor Gómez García 0690a948f2 Improve clock accuracy by separating system clocks into dedicated PLL ...

- Extract system clocks (clk_28_636, clk_4_77) from main PLL into new
  pll_system module (General PLL, no reconfig); clk_14_318 and
  peripheral_clock remain as software toggles derived from those two
- Simplify main PLL: now outputs only clk_100 and clk_chipset (50 MHz),
  both reconfigurable as before
- Remove dead clocks whose casez branches were unreachable (clk_select is
  hardwired to 2'b00): clk_9_54, clk_7_16, clk_25 and their generators
- Delete clk_div3 module (rtl/common/clk_div3.v) — no remaining
  instantiation; convert six formerly casez-derived signals to wire
  constants so the synthesizer can optimise them away
- Route CLK_VIDEO and CLK_VIDEO_CGA to clk_28_636 (2× CGA pixel clock,
  sufficient for the scandoubler); UART sync samples clk_14_318 through
  three FFs into clk_chipset domain
- Update SYSTEM.sdc: declare both PLLs, add generated-clock specs for the
  two software toggles, and set bidirectional false paths for all
  asynchronous clock-domain crossings between them

2026-02-08 07:35:59 +01:00

..

pll_0002.qip

Initial commit

2026-01-06 11:36:45 +01:00

pll_0002.v

Improve clock accuracy by separating system clocks into dedicated PLL

2026-02-08 07:35:59 +01:00