This file runs a simulation on the purely combinational logic of the envelope generator.
The simulation is controlled via text files

The text file is a sequence of write commands that will configure the inputs to the logic
then a wait command will kick the simulation for a given number of clocks. Test files
are stored in the tests folder.

The LFO is always running. The simulations show that SSG is well implemented and that
the circuit behaves within bounds for extreme cases

The core logic of the ASDR envelope is simulated on separate test bench eg2.

Arguments:
	-w write VCD	(always enabled, uncomment to evaluate this argument)
	-f path-to-test-file