mirror of
https://github.com/MiSTer-devel/PCXT_MiSTer.git
synced 2026-04-19 03:04:47 +00:00
6decefa0f8
- Extract system clocks (clk_28_636, clk_57_272, clk_114_544, clk_9_54, clk_7_16, clk_4_77) from main PLL to new pll_system module for improved frequency precision - Simplify main PLL: now outputs only clk_100 (100 MHz) and clk_chipset (50 MHz) - Replace integer divider chains with dedicated PLL outputs for better timing accuracy - Remove clk_div3 logic and generate clock dividers directly from PLL - New pll_system uses lower VCO frequency (300 MHz vs 1600 MHz) for better stability - Update SYSTEM.sdc timing constraints for new clock distribution - Reduces jitter and improves timing closure for sensitive subsystems
193 lines
12 KiB
Tcl
193 lines
12 KiB
Tcl
derive_pll_clocks
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derive_clock_uncertainty
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# core specific constraints
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# Clocks - PLL principal (Chipset/SDRAM domain)
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set CLOCK_CORE {emu|pll|pll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}
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set CLOCK_CHIP {emu|pll|pll_inst|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk}
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# Clocks - PLL video (CPU/Video domain - precise frequencies)
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set CLOCK_VGA_CGA {emu|pll_system_inst|pll_system_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}
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set CLOCK_VGA_MDA {emu|pll_system_inst|pll_system_inst|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk}
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set CLOCK_VIDEO_MDA {emu|pll_system_inst|pll_system_inst|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk}
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set CLOCK_9_54 {emu|pll_system_inst|pll_system_inst|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk}
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set CLOCK_7_16 {emu|pll_system_inst|pll_system_inst|altera_pll_i|cyclonev_pll|counter[4].output_counter|divclk}
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set CLOCK_4_77 {emu|pll_system_inst|pll_system_inst|altera_pll_i|cyclonev_pll|counter[5].output_counter|divclk}
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# Derived clocks (from PLL video domain)
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set CLOCK_14_318 {emu|clk_14_318|q}
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set PCLK {emu|peripheral_clock|q}
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# clk_14_318 derives from clk_28_636 (PLL video - precise frequency)
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create_generated_clock -name clk_14_318 -source [get_pins $CLOCK_VGA_CGA] -divide_by 2 [get_pins $CLOCK_14_318]
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create_generated_clock -name peripheral_clock -source [get_pins $CLOCK_4_77] -divide_by 2 [get_pins $PCLK]
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create_generated_clock -name SDRAM_CLK -source [get_pins $CLOCK_CHIP] [get_ports { SDRAM_CLK }]
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create_clock -name VCLK_SDIO -period 20.000
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# SPLASH
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set_false_path -to [get_registers {emu:emu|splash_off}]
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# CDC: PLL principal (Chipset) <-> PLL video (CPU/Video) - asynchronous clock domains
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set_false_path -from [get_clocks $CLOCK_CHIP] -to [get_clocks $CLOCK_VGA_CGA]
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set_false_path -from [get_clocks $CLOCK_VGA_CGA] -to [get_clocks $CLOCK_CHIP]
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set_false_path -from [get_clocks $CLOCK_CHIP] -to [get_clocks $CLOCK_VGA_MDA]
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set_false_path -from [get_clocks $CLOCK_VGA_MDA] -to [get_clocks $CLOCK_CHIP]
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set_false_path -from [get_clocks $CLOCK_CHIP] -to [get_clocks $CLOCK_VIDEO_MDA]
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set_false_path -from [get_clocks $CLOCK_VIDEO_MDA] -to [get_clocks $CLOCK_CHIP]
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set_false_path -from [get_clocks $CLOCK_CHIP] -to [get_clocks $CLOCK_9_54]
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set_false_path -from [get_clocks $CLOCK_9_54] -to [get_clocks $CLOCK_CHIP]
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set_false_path -from [get_clocks $CLOCK_CHIP] -to [get_clocks $CLOCK_7_16]
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set_false_path -from [get_clocks $CLOCK_7_16] -to [get_clocks $CLOCK_CHIP]
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set_false_path -from [get_clocks $CLOCK_CHIP] -to [get_clocks $CLOCK_4_77]
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set_false_path -from [get_clocks $CLOCK_4_77] -to [get_clocks $CLOCK_CHIP]
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set_false_path -from [get_clocks $CLOCK_CHIP] -to [get_clocks clk_14_318]
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set_false_path -from [get_clocks clk_14_318] -to [get_clocks $CLOCK_CHIP]
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set_false_path -from [get_clocks $CLOCK_CHIP] -to [get_clocks peripheral_clock]
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set_false_path -from [get_clocks peripheral_clock] -to [get_clocks $CLOCK_CHIP]
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set_false_path -from [get_clocks $CLOCK_CORE] -to [get_clocks $CLOCK_VGA_CGA]
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set_false_path -from [get_clocks $CLOCK_VGA_CGA] -to [get_clocks $CLOCK_CORE]
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set_false_path -from [get_clocks $CLOCK_CORE] -to [get_clocks $CLOCK_4_77]
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set_false_path -from [get_clocks $CLOCK_4_77] -to [get_clocks $CLOCK_CORE]
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set_false_path -from [get_clocks $CLOCK_CORE] -to [get_clocks clk_14_318]
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set_false_path -from [get_clocks clk_14_318] -to [get_clocks $CLOCK_CORE]
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# VIDEO
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# NOTE: If the system clock and video clock are synchronous, the following description is not necessary.
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set VIDEO_TO_SYSYEM_DELAY 10
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set_false_path -to [get_registers {emu:emu|scale_video_ff[*] \
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emu:emu|mda_mode_video_ff \
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emu:emu|screen_mode_video_ff[*] \
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emu:emu|border_video_ff \
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emu:emu|VIDEO_ARX[*] \
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emu:emu|VIDEO_ARY[*]}]
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set_max_delay -from [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|video_io_address[*]}] \
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-to [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|mda_io_address_1[*] \
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emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|cga_io_address_1[*]}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -from [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|video_io_data[*]}] \
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-to [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|mda_io_data_1[*] \
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emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|cga_io_data_1[*]}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -from [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|video_io_write_n}] \
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-to [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|mda_io_write_n_1 \
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emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|cga_io_write_n_1}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -from [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|video_io_read_n}] \
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-to [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|mda_io_read_n_1 \
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emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|cga_io_read_n_1}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -from [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|video_address_enable_n}] \
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-to [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|mda_address_enable_n_1 \
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emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|cga_address_enable_n_1}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -to [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|MDA_CRTC_DOUT_1[*] \
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emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|MDA_CRTC_OE_1 \
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emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|CGA_CRTC_DOUT_1[*] \
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emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|CGA_CRTC_OE_1}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -from [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|video_io_address[*]}] \
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-to [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|hgc_io_address_1[*]}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -from [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|video_io_data[*]}] \
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-to [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|hgc_io_data_1[*]}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -from [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|video_io_read_n}] \
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-to [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|hgc_io_read_n_1}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -from [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|video_io_write_n}] \
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-to [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|hgc_io_write_n_1}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -from [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|video_address_enable_n}] \
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-to [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|hgc_address_enable_n_1}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -from [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|hgc:hgc1|hgc_control_reg[*]}] \
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-to [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|data_bus_out[*] \
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emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|data_bus_out_from_chipset}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -to [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|HGC_CRTC_DOUT_1[*] \
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emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|HGC_CRTC_OE_1}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -from [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|hgc:hgc1|hgc_control_reg[7]}] \
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-to [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|vram:hgc_vram|* \
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emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|hgc_mem_select_1}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -from [get_registers {emu:emu|hps_io:hps_io|video_calc:video_calc|vid_hcnt[*] \
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emu:emu|hps_io:hps_io|video_calc:video_calc|vid_nres[*] \
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emu:emu|hps_io:hps_io|video_calc:video_calc|vid_vcnt[*]}] \
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-to [get_registers {emu:emu|hps_io:hps_io|video_calc:video_calc|dout[*]}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -from [get_registers {emu:emu|mda_mode_video_ff}] \
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-to [get_registers {emu:emu|hps_io:hps_io|io_dout[0]}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -from [get_registers {emu:emu|scale_video_ff[*]}] \
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-to [get_registers {sl_r[*] \
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emu:emu|video_mixer:video_mixer_mda|CE_PIXEL}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -to [get_registers {emu:emu|cga_hw}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -to [get_registers {emu:emu|hercules_hw}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -to [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|swap_video_buffer_2}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -to [get_registers {emu:emu|video_pause_core_buf}] $VIDEO_TO_SYSYEM_DELAY
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#
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set_max_delay -from [get_registers {osd:vga_osd|info \
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osd:vga_osd|infoh[*] \
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osd:vga_osd|osd_h[*] \
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osd:vga_osd|osd_w[*]}] \
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-to [get_registers {osd:vga_osd|osd_de[*] \
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osd:vga_osd|osd_hcnt2[*]}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -from [get_registers {osd:vga_osd|osd_enable}] \
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-to [get_registers {osd:vga_osd|osd_en[*]}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -from [get_registers {lowlat}] \
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-to [get_registers {ascal:ascal|i_mode[*]}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -from [get_registers {LFB_FLT}] \
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-to [get_registers {ascal:ascal|i_mode[2]}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -from [get_registers {LFB_EN}] \
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-to [get_registers {hmaxi[*] \
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hmini[*] \
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state[0] \
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state[1] \
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state[2] \
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vmaxi[*] \
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vmini[*] \
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ascal:ascal|i_mode[2]}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -from [get_registers {FREESCALE}] \
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-to [get_registers {state[0] \
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state[1] \
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state[2]}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -from [get_registers {HDMI_PR}] \
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-to [get_registers {videow[*]}] $VIDEO_TO_SYSYEM_DELAY
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set_max_delay -from [get_registers {cfg_done}] \
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-to [get_registers {pll_hdmi_adj:pll_hdmi_adj|i_delay[*] \
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pll_hdmi_adj:pll_hdmi_adj|i_de2 \
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pll_hdmi_adj:pll_hdmi_adj|i_line[*] \
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pll_hdmi_adj:pll_hdmi_adj|i_linecpt[*] \
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pll_hdmi_adj:pll_hdmi_adj|i_vss_delay \
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pll_hdmi_adj:pll_hdmi_adj|i_vss2}] $VIDEO_TO_SYSYEM_DELAY
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# SDIO
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set_input_delay -clock { VCLK_SDIO } -max 10 [get_ports { SDIO_DAT[*] SDIO_CMD }]
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set_input_delay -clock { VCLK_SDIO } -min 5 [get_ports { SDIO_DAT[*] SDIO_CMD }]
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set_output_delay -clock { VCLK_SDIO } -max 5 [get_ports { SDIO_DAT[*] SDIO_CMD SDIO_CLK }]
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set_output_delay -clock { VCLK_SDIO } -min 0 [get_ports { SDIO_DAT[*] SDIO_CMD SDIO_CLK }]
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# SDRAM
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set_input_delay -clock { SDRAM_CLK } -max 6 [get_ports { SDRAM_DQ[*] }]
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set_input_delay -clock { SDRAM_CLK } -min 3 [get_ports { SDRAM_DQ[*] }]
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set_output_delay -clock { SDRAM_CLK } -max 2 [get_ports { SDRAM_DQ[*] SDRAM_DQM* SDRAM_A[*] SDRAM_n* SDRAM_BA[*] SDRAM_CKE }]
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set_output_delay -clock { SDRAM_CLK } -min 1.5 [get_ports { SDRAM_DQ[*] SDRAM_DQM* SDRAM_A[*] SDRAM_n* SDRAM_BA[*] SDRAM_CKE }]
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