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14 lines
1.1 KiB
Plaintext
14 lines
1.1 KiB
Plaintext
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) slib_clock_div.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) slib_counter.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) slib_edge_detect.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) slib_fifo.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) slib_input_filter.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) slib_input_sync.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) slib_mv_filter.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) uart_16750.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) uart_baudgen.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) uart_interrupt.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) uart_receiver.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) uart_transmitter.vhd ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) uart.v ]
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