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103 lines
4.0 KiB
VHDL
103 lines
4.0 KiB
VHDL
--
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-- UART interrupt control
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--
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-- Author: Sebastian Witt
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-- Date: 27.01.2008
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-- Version: 1.1
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--
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-- History: 1.0 - Initial version
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-- 1.1 - Automatic flow control
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--
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--
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-- This code is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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--
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-- This code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the
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-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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-- Boston, MA 02111-1307 USA
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--
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.all;
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USE IEEE.numeric_std.all;
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-- Serial UART interrupt control
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entity uart_interrupt is
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port (
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CLK : in std_logic; -- Clock
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RST : in std_logic; -- Reset
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IER : in std_logic_vector(3 downto 0); -- IER 3:0
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LSR : in std_logic_vector(4 downto 0); -- LSR 4:0
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THI : in std_logic; -- Transmitter holding register empty interrupt
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RDA : in std_logic; -- Receiver data available
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CTI : in std_logic; -- Character timeout indication
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AFE : in std_logic; -- Automatic flow control enable
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MSR : in std_logic_vector(3 downto 0); -- MSR 3:0
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IIR : out std_logic_vector(3 downto 0); -- IIR 3:0
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INT : out std_logic -- Interrupt
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);
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end uart_interrupt;
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architecture rtl of uart_interrupt is
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-- Signals
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signal iRLSInterrupt : std_logic; -- Receiver line status interrupt
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signal iRDAInterrupt : std_logic; -- Received data available interrupt
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signal iCTIInterrupt : std_logic; -- Character timeout indication interrupt
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signal iTHRInterrupt : std_logic; -- Transmitter holding register empty interrupt
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signal iMSRInterrupt : std_logic; -- Modem status interrupt
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signal iIIR : std_logic_vector(3 downto 0); -- IIR register
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begin
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-- Priority 1: Receiver line status interrupt on: Overrun error, parity error, framing error or break interrupt
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iRLSInterrupt <= IER(2) and (LSR(1) or LSR(2) or LSR(3) or LSR(4));
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-- Priority 2: Received data available or trigger level reached in FIFO mode
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iRDAInterrupt <= IER(0) and RDA;
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-- Priority 2: Character timeout indication
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iCTIInterrupt <= IER(0) and CTI;
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-- Priority 3: Transmitter holding register empty
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iTHRInterrupt <= IER(1) and THI;
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-- Priority 4: Modem status interrupt: dCTS (when AFC is disabled), dDSR, TERI, dDCD
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iMSRInterrupt <= IER(3) and ((MSR(0) and not AFE) or MSR(1) or MSR(2) or MSR(3));
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-- IIR
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IC_IIR: process (CLK, RST)
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begin
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if (RST = '1') then
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iIIR <= "0001"; -- TODO: Invert later
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elsif (CLK'event and CLK = '1') then
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-- IIR register
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if (iRLSInterrupt = '1') then
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iIIR <= "0110";
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elsif (iCTIInterrupt = '1') then
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iIIR <= "1100";
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elsif (iRDAInterrupt = '1') then
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iIIR <= "0100";
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elsif (iTHRInterrupt = '1') then
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iIIR <= "0010";
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elsif (iMSRInterrupt = '1') then
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iIIR <= "0000";
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else
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iIIR <= "0001";
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end if;
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end if;
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end process;
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-- Outputs
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IIR <= iIIR;
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INT <= not iIIR(0);
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end rtl;
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