Aitor Gómez García 1b5c54c058 Video: retime exact-frequency CGA/HGC output onto HDMI clocks ...

Move the final CGA and HGC/MDA export off the raw exact-frequency video domains and retime it onto a phase-shifted 57.272727 MHz sibling clock, while keeping the internal 28.636363/57.272727/114.545454 MHz clocks exact.

Derive the 9.54/7.16/4.77 MHz clocks locally from clk_57_272, feed the final CE_PIXEL and overlay path from the retimed output stage, and add explicit timing constraints for the handoff into the phase-shifted video clock domain.

2026-03-12 08:50:35 +01:00

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pll_system_0002.qip

Improve clock accuracy by separating system clocks into dedicated PLL

2026-01-23 13:42:58 +01:00

pll_system_0002.v

Video: retime exact-frequency CGA/HGC output onto HDMI clocks

2026-03-12 08:50:35 +01:00