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6decefa0f8
- Extract system clocks (clk_28_636, clk_57_272, clk_114_544, clk_9_54, clk_7_16, clk_4_77) from main PLL to new pll_system module for improved frequency precision - Simplify main PLL: now outputs only clk_100 (100 MHz) and clk_chipset (50 MHz) - Replace integer divider chains with dedicated PLL outputs for better timing accuracy - Remove clk_div3 logic and generate clock dividers directly from PLL - New pll_system uses lower VCO frequency (300 MHz vs 1600 MHz) for better stability - Update SYSTEM.sdc timing constraints for new clock distribution - Reduces jitter and improves timing closure for sensitive subsystems