15 Commits

Author	SHA1	Message	Date
kitune-san	212900dc71	Added MMC drive.	2023-04-27 01:43:56 +09:00
kitune-san	dc54db83f2	Eliminate some timing errors.	2023-04-17 23:40:04 +09:00
somhi	52295db8cf	minor	2023-04-01 15:06:42 +02:00
Gyorgy Szombathelyi	5fc54a6d3f	Clocking cleanup ... - Remove some unnecessary clock domain crossings - Generate the opl2_cen in the clk_chipset domain - Fix the rate which used to calculate fractional CE's, SAA(CMS) tone pitch is now correct	2023-04-01 14:42:05 +02:00
kitune-san	26692f3574	Eliminate some timing errors.	2022-11-13 00:07:47 +09:00
birdybro	d94aacf0ce	Resolve some warnings and update gitignore	2022-08-19 22:40:40 -06:00
kitune-san	822be93e1c	Fix SDRAM input_delay mistake.	2022-08-18 19:15:21 +09:00
kitune-san	eaba318d41	Improved access speed to SDRAM.	2022-08-15 13:07:19 +09:00
Aitor Gómez	afd39c8dab	changed chipset clock to 50 mhz and rework (by @kitune-san) ... * changed chipset clock to 50 mhz. * Added false_path. * Change peripheral_clock signal. * Added F/F to the write process to the EMS memory to resolve timing co… * Add 2-stage F/F between bus and video module. * Changed 8253 timer_clock signal. * Fixed F/F clocks.	2022-08-04 07:55:09 +02:00
Aitor Gómez	8320ad0036	Simple improvements to PCXT.sdc	2022-07-10 07:01:24 +02:00
Aitor Gómez	81e341ebac	Fix timmings in PCXT.sdc	2022-07-01 06:32:17 +02:00
somhi	b6685bea68	PR to mister branch	2022-06-26 01:38:04 +02:00
kitune-san	b8a1e2763b	Update PCXT.sdc.	2022-06-18 23:16:29 +09:00
Aitor Gómez	5dedaacc12	Beta 0.9 ... * Add SDRAM module, by @kitune-san	2022-06-18 10:01:00 +02:00
Aitor Gómez	b66b2c81c0	Initial version ... Unstable version: * Hardware interrupts are not executed. * No VHD or SD support. * BASIC ROM execution set in the BIOS, before the OS load routine.	2022-05-09 17:36:26 +02:00