From afd39c8dabda7cefd6918e644c4964450f37aade Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Aitor=20G=C3=B3mez?= Date: Thu, 4 Aug 2022 07:55:09 +0200 Subject: [PATCH] changed chipset clock to 50 mhz and rework (by @kitune-san) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * changed chipset clock to 50 mhz. * Added false_path. * Change peripheral_clock signal. * Added F/F to the write process to the EMS memory to resolve timing co… * Add 2-stage F/F between bus and video module. * Changed 8253 timer_clock signal. * Fixed F/F clocks. --- PCXT.sdc | 36 ++++++- PCXT.sv | 33 +++--- rtl/KFPC-XT/HDL/Peripherals.sv | 182 +++++++++++++++++++++++++++------ rtl/pll.qip | 22 ++-- rtl/pll.v | 6 +- rtl/pll/pll_0002.v | 15 +-- 6 files changed, 230 insertions(+), 64 deletions(-) diff --git a/PCXT.sdc b/PCXT.sdc index 8034684..de0a901 100644 --- a/PCXT.sdc +++ b/PCXT.sdc @@ -4,6 +4,8 @@ derive_clock_uncertainty # core specific constraints # Clocks set CLOCK_CORE {emu|pll|pll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk} +set CLOCK_CHIP {emu|pll|pll_inst|altera_pll_i|cyclonev_pll|counter[5].output_counter|divclk} +set CLOCK_UART {emu|pll|pll_inst|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk} set CLOCK_14_318 {emu|clk_14_318|q} set CLOCK_4_77 {emu|clk_normal|clk_out|q} set PCLK {emu|peripheral_clock|q} @@ -11,10 +13,42 @@ set PCLK {emu|peripheral_clock|q} create_generated_clock -name clk_14_318 -source [get_pins {emu|pll|pll_inst|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk}] -divide_by 2 [get_pins $CLOCK_14_318] create_generated_clock -name clk_4_77 -source [get_pins $CLOCK_14_318] -divide_by 3 -duty_cycle 33 [get_pins $CLOCK_4_77] create_generated_clock -name peripheral_clock -source [get_pins $CLOCK_4_77] -divide_by 2 [get_pins $PCLK] -create_generated_clock -name SDRAM_CLK -source { FPGA_CLK2_50 } [get_ports { SDRAM_CLK }] +create_generated_clock -name SDRAM_CLK -source [get_pins $CLOCK_CHIP] [get_ports { SDRAM_CLK }] + +set_false_path -to [get_registers {emu:emu|clk_cpu_ff_1 emu:emu|pclk_ff_1 emu:emu|clk_opl2_ff_1}] + +# status signal +set_false_path -from [get_registers {emu:emu|hps_io:hps_io|status[3] emu:emu|hps_io:hps_io|status[4] emu:emu|hps_io:hps_io|status[7]}] + +# UART +set_false_path -from [get_clocks $CLOCK_CHIP] -to [get_clocks $CLOCK_UART] +set_false_path -from [get_clocks $CLOCK_UART] -to [get_clocks $CLOCK_CHIP] + +# VIDEO +set_max_delay -from [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|video_io_address[*] \ + emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|video_io_data[*] \ + emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|video_io_write_n \ + emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|video_io_read_n \ + emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|video_address_enable_n}] \ + -to [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|mda_io_address_1[*] \ + emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|mda_io_data_1[*] \ + emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|mda_io_write_n_1 \ + emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|mda_io_read_n_1 \ + emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|mda_address_enable_n_1 \ + emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|cga_io_address_1[*] \ + emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|cga_io_data_1[*] \ + emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|cga_io_write_n_1 \ + emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|cga_io_read_n_1 \ + emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|cga_address_enable_n_1}] 10 + +set_max_delay -to [get_registers {emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|MDA_CRTC_DOUT_1[*] \ + emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|MDA_CRTC_OE_1 \ + emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|CGA_CRTC_DOUT_1[*] \ + emu:emu|CHIPSET:u_CHIPSET|PERIPHERALS:u_PERIPHERALS|CGA_CRTC_OE_1}] 10 # SDRAM set_input_delay -clock { SDRAM_CLK } -max 6 [get_ports { SDRAM_DQ[*] }] set_input_delay -clock { SDRAM_CLK } -min 3 [get_ports { SDRAM_DQ[*] }] set_output_delay -clock { SDRAM_CLK } -max 2 [get_ports { SDRAM_DQ[*] SDRAM_DQM* SDRAM_A[*] SDRAM_n* SDRAM_BA[*] SDRAM_CKE }] set_output_delay -clock { SDRAM_CLK } -min 1.5 [get_ports { SDRAM_DQ[*] SDRAM_DQM* SDRAM_A[*] SDRAM_n* SDRAM_BA[*] SDRAM_CKE }] + diff --git a/PCXT.sv b/PCXT.sv index be86545..d96a86f 100644 --- a/PCXT.sv +++ b/PCXT.sv @@ -178,7 +178,7 @@ assign USER_OUT = '1; //assign {UART_RTS, UART_TXD, UART_DTR} = 0; //assign {SD_SCK, SD_MOSI, SD_CS} = 'Z; //assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z; -assign SDRAM_CLK = CLK_50M; +assign SDRAM_CLK = clk_chipset; assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = '0; @@ -292,7 +292,7 @@ wire adlibhide = status[10]; hps_io #(.CONF_STR(CONF_STR), .PS2DIV(2000), .PS2WE(1)) hps_io ( - .clk_sys(CLK_50M), + .clk_sys(clk_chipset), .HPS_BUS(HPS_BUS), .EXT_BUS(), .gamma_bus(gamma_bus), @@ -346,7 +346,9 @@ reg clk_14_318 = 1'b0; reg clk_7_16 = 1'b0; wire clk_4_77; wire clk_cpu; +wire pclk; wire clk_opl2; +wire clk_chipset; wire peripheral_clock; pll pll @@ -358,6 +360,7 @@ pll pll .outclk_2(clk_28_636), .outclk_3(clk_uart), .outclk_4(clk_opl2), + .outclk_5(clk_chipset), .locked(pll_locked) ); @@ -407,10 +410,16 @@ always @(posedge clk_4_77) logic clk_cpu_ff_1; logic clk_cpu_ff_2; -always @(posedge clk_100) begin +logic pclk_ff_1; +logic pclk_ff_2; + +always @(posedge clk_chipset) begin clk_cpu_ff_1 <= clk_4_77; clk_cpu_ff_2 <= clk_cpu_ff_1; clk_cpu <= clk_cpu_ff_2; + pclk_ff_1 <= peripheral_clock; + pclk_ff_2 <= pclk_ff_1; + pclk <= pclk_ff_2; end logic clk_opl2_ff_1; @@ -418,7 +427,7 @@ logic clk_opl2_ff_2; logic clk_opl2_ff_3; logic cen_opl2; -always @(posedge clk_100) begin +always @(posedge clk_chipset) begin clk_opl2_ff_1 <= clk_opl2; clk_opl2_ff_2 <= clk_opl2_ff_1; clk_opl2_ff_3 <= clk_opl2_ff_2; @@ -456,14 +465,14 @@ logic reset_cpu_ff = 1'b1; logic reset_cpu = 1'b1; logic [15:0] reset_cpu_count = 16'h0000; -always @(negedge clk_100, posedge reset) begin +always @(negedge clk_chipset, posedge reset) begin if (reset) reset_cpu_ff <= 1'b1; else reset_cpu_ff <= reset; end -always @(negedge clk_100, posedge reset) begin +always @(negedge clk_chipset, posedge reset) begin if (reset) begin reset_cpu <= 1'b1; reset_cpu_count <= 16'h0000; @@ -518,7 +527,7 @@ end logic device_clock_ff; logic device_clock; - always_ff @(negedge clk_cpu, posedge reset) + always_ff @(negedge clk_chipset, posedge reset) begin if (reset) begin device_clock_ff <= 1'b0; @@ -537,7 +546,7 @@ end logic device_data_ff; logic device_data; - always_ff @(negedge clk_cpu, posedge reset) + always_ff @(negedge clk_chipset, posedge reset) begin if (reset) begin device_data_ff <= 1'b0; @@ -575,10 +584,10 @@ end assign port_c_in[3:0] = port_b_out[3] ? sw[7:4] : sw[3:0]; CHIPSET u_CHIPSET ( - .clock (clk_100), + .clock (clk_chipset), .cpu_clock (clk_cpu), - .clk_sys (CLK_50M), - .peripheral_clock (peripheral_clock), + .clk_sys (clk_chipset), + .peripheral_clock (pclk), .reset (reset_cpu), .sdram_reset (reset), @@ -733,7 +742,7 @@ end wire uart_dsr = UART_DSR; wire uart_dcd = UART_DTR; - always @(posedge clk_cpu) begin + always @(posedge clk_100) begin if (address_latch_enable) cpu_address <= cpu_ad_out; else diff --git a/rtl/KFPC-XT/HDL/Peripherals.sv b/rtl/KFPC-XT/HDL/Peripherals.sv index 522451c..fc24dd6 100644 --- a/rtl/KFPC-XT/HDL/Peripherals.sv +++ b/rtl/KFPC-XT/HDL/Peripherals.sv @@ -146,15 +146,36 @@ module PERIPHERALS #( assign ems_b3 = (~iorq && ena_ems[2] && (address[19:14] == {ems_page_address, 2'b10})); // A8000h - C8000h - D8000h assign ems_b4 = (~iorq && ena_ems[3] && (address[19:14] == {ems_page_address, 2'b11})); // AC000h - CC000h - DC000h + + logic [1:0] ems_access_address; + logic ems_write_enable; + logic [7:0] write_map_ems_data; + logic write_map_ena_data; + + always_ff @(posedge clock, posedge reset) begin + if (reset) begin + ems_access_address <= 2'b11; + ems_write_enable <= 1'b0; + write_map_ems_data <= 1'b0; + write_map_ena_data <= 1'b0; + end + else begin + ems_access_address <= address[1:0]; + ems_write_enable <= ems_oe && ~io_write_n; + write_map_ems_data <= (internal_data_bus == 8'hFF) ? 7'hFF : (internal_data_bus < 8'h80) ? internal_data_bus[6:0] : map_ems[address[1:0]]; + write_map_ena_data <= (internal_data_bus == 8'hFF) ? 1'b0 : (internal_data_bus < 8'h80) ? 1'b1 : ena_ems[address[1:0]]; + end + end + always_ff @(posedge clock, posedge reset) begin if (reset) begin map_ems = '{7'h00, 7'h00, 7'h00, 7'h00}; ena_ems = '{1'b0, 1'b0, 1'b0, 1'b0}; end - else if (ems_oe && ~io_write_n) begin - map_ems[address[1:0]] <= (internal_data_bus == 8'hFF) ? 7'hFF : (internal_data_bus < 8'h80) ? internal_data_bus[6:0] : map_ems[address[1:0]]; - ena_ems[address[1:0]] <= (internal_data_bus == 8'hFF) ? 1'b0 : (internal_data_bus < 8'h80) ? 1'b1 : ena_ems[address[1:0]]; + else if (ems_write_enable) begin + map_ems[ems_access_address] <= write_map_ems_data; + ena_ems[ems_access_address] <= write_map_ena_data; end end @@ -193,28 +214,32 @@ module PERIPHERALS #( // // 8253 // - // Clock domain crossing - logic timer_clock_ff_1; - always_ff @(posedge peripheral_clock, posedge reset) begin - if (reset) - timer_clock_ff_1 <= 1'b0; - else - timer_clock_ff_1 <= ~timer_clock_ff_1; - end - - logic timer_clock_ff_2; - logic timer_clock; + logic prev_p_clock_1; + logic prev_p_clock_2; always_ff @(posedge clock, posedge reset) begin if (reset) begin - timer_clock_ff_2 <= 1'b0; - timer_clock <= 1'b0; + prev_p_clock_1 <= 1'b0; + prev_p_clock_2 <= 1'b0; end else begin - timer_clock_ff_2 <= timer_clock_ff_1; - timer_clock <= timer_clock_ff_2; + prev_p_clock_1 <= peripheral_clock; + prev_p_clock_2 <= prev_p_clock_1; + end end + wire p_clock_posedge = prev_p_clock_1 & ~prev_p_clock_2; + + logic timer_clock; + always_ff @(posedge clock, posedge reset) begin + if (reset) + timer_clock <= 1'b0; + else if (p_clock_posedge) + timer_clock <= ~timer_clock; + else + timer_clock <= timer_clock; + end + logic [7:0] timer_data_bus_out; wire tim2gatespk = port_b_out[0] & ~port_b_io; @@ -482,6 +507,76 @@ module PERIPHERALS #( else uart_readdata <= uart_readdata; end + + + logic [14:0] video_io_address; + logic [7:0] video_io_data; + logic video_io_write_n; + logic video_io_read_n; + logic video_address_enable_n; + logic [14:0] mda_io_address_1; + logic [14:0] mda_io_address_2; + logic [7:0] mda_io_data_1; + logic [7:0] mda_io_data_2; + logic mda_io_write_n_1; + logic mda_io_write_n_2; + logic mda_io_write_n_3; + logic mda_io_read_n_1; + logic mda_io_read_n_2; + logic mda_io_read_n_3; + logic mda_address_enable_n_1; + logic mda_address_enable_n_2; + logic [14:0] cga_io_address_1; + logic [14:0] cga_io_address_2; + logic [7:0] cga_io_data_1; + logic [7:0] cga_io_data_2; + logic cga_io_write_n_1; + logic cga_io_write_n_2; + logic cga_io_write_n_3; + logic cga_io_read_n_1; + logic cga_io_read_n_2; + logic cga_io_read_n_3; + logic cga_address_enable_n_1; + logic cga_address_enable_n_2; + + always_ff @(posedge clock) begin + video_io_address <= address[14:0]; + video_io_data <= internal_data_bus; + video_io_write_n <= io_write_n; + video_io_read_n <= io_read_n; + video_address_enable_n <= address_enable_n; + end + + always_ff @(posedge clk_vga_mda) begin + mda_io_address_1 <= video_io_address; + mda_io_address_2 <= mda_io_address_1; + mda_io_data_1 <= video_io_data; + mda_io_data_2 <= mda_io_data_1; + mda_io_write_n_1 <= video_io_write_n; + mda_io_write_n_2 <= mda_io_write_n_1; + mda_io_write_n_3 <= mda_io_write_n_2; + mda_io_read_n_1 <= video_io_read_n; + mda_io_read_n_2 <= mda_io_read_n_1; + mda_io_read_n_3 <= mda_io_read_n_2; + mda_address_enable_n_1 <= video_address_enable_n; + mda_address_enable_n_2 <= mda_address_enable_n_1; + end + + always_ff @(posedge clk_vga_cga) begin + cga_io_address_1 <= video_io_address; + cga_io_address_2 <= cga_io_address_1; + cga_io_data_1 <= video_io_data; + cga_io_data_2 <= cga_io_data_1; + cga_io_write_n_1 <= video_io_write_n; + cga_io_write_n_2 <= cga_io_write_n_1; + cga_io_write_n_3 <= cga_io_write_n_2; + cga_io_read_n_1 <= video_io_read_n; + cga_io_read_n_2 <= cga_io_read_n_1; + cga_io_read_n_3 <= cga_io_read_n_2; + cga_address_enable_n_1 <= video_address_enable_n; + cga_address_enable_n_2 <= cga_address_enable_n_1; + end + reg [5:0] R_CGA; reg [5:0] G_CGA; @@ -521,7 +616,11 @@ module PERIPHERALS #( wire [18:0] MDA_VRAM_ADDR; wire [7:0] MDA_VRAM_DOUT; wire MDA_CRTC_OE; + wire MDA_CRTC_OE_1; + wire MDA_CRTC_OE_2; wire [7:0] MDA_CRTC_DOUT; + wire [7:0] MDA_CRTC_DOUT_1; + wire [7:0] MDA_CRTC_DOUT_2; wire intensity; @@ -539,15 +638,15 @@ module PERIPHERALS #( mda mda1 ( .clk (clk_vga_mda), - .bus_a (address[14:0]), - .bus_ior_l (io_read_n), - .bus_iow_l (io_write_n), + .bus_a (mda_io_address_2), + .bus_ior_l (mda_io_read_n_3), + .bus_iow_l (mda_io_write_n_3), .bus_memr_l (1'd0), .bus_memw_l (1'd0), - .bus_d (internal_data_bus), + .bus_d (mda_io_data_2), .bus_out (MDA_CRTC_DOUT), .bus_dir (MDA_CRTC_OE), - .bus_aen (address_enable_n), + .bus_aen (mda_address_enable_n_2), .ram_we_l (MDA_VRAM_ENABLE), .ram_a (MDA_VRAM_ADDR), .ram_d (MDA_VRAM_DOUT), @@ -559,13 +658,24 @@ module PERIPHERALS #( .video (video_mda), .de_o (de_o_mda) ); + + always_ff @(posedge clock) begin + MDA_CRTC_DOUT_1 <= MDA_CRTC_DOUT; + MDA_CRTC_DOUT_2 <= MDA_CRTC_DOUT_1; + MDA_CRTC_OE_1 <= MDA_CRTC_OE; + MDA_CRTC_OE_2 <= MDA_CRTC_OE_1; + end wire CGA_VRAM_ENABLE; wire [18:0] CGA_VRAM_ADDR; wire [7:0] CGA_VRAM_DOUT; wire CGA_CRTC_OE; + wire CGA_CRTC_OE_1; + wire CGA_CRTC_OE_2; wire [7:0] CGA_CRTC_DOUT; + wire [7:0] CGA_CRTC_DOUT_1; + wire [7:0] CGA_CRTC_DOUT_2; // Sets up the card to generate a video signal // that will work with a standard VGA monitor @@ -595,15 +705,15 @@ module PERIPHERALS #( cga cga1 ( .clk (clk_vga_cga), - .bus_a (address[14:0]), - .bus_ior_l (io_read_n), - .bus_iow_l (io_write_n), + .bus_a (cga_io_address_2), + .bus_ior_l (cga_io_read_n_3), + .bus_iow_l (cga_io_write_n_3), .bus_memr_l (1'd0), .bus_memw_l (1'd0), - .bus_d (internal_data_bus), + .bus_d (cga_io_data_2), .bus_out (CGA_CRTC_DOUT), .bus_dir (CGA_CRTC_OE), - .bus_aen (address_enable_n), + .bus_aen (cga_address_enable_n_2), .ram_we_l (CGA_VRAM_ENABLE), .ram_a (CGA_VRAM_ADDR), .ram_d (CGA_VRAM_DOUT), @@ -620,6 +730,14 @@ module PERIPHERALS #( .tandy_video (tandy_video) ); + always_ff @(posedge clock) begin + CGA_CRTC_OE_1 <= CGA_CRTC_OE; + CGA_CRTC_OE_2 <= CGA_CRTC_OE_1; + CGA_CRTC_DOUT_1 <= CGA_CRTC_DOUT; + CGA_CRTC_DOUT_2 <= CGA_CRTC_DOUT_1; + end + + defparam cga1.BLINK_MAX = 24'd4772727; defparam mda1.BLINK_MAX = 24'd9100000; wire [7:0] bios_cpu_dout; @@ -750,13 +868,13 @@ module PERIPHERALS #( data_bus_out_from_chipset = 1'b1; data_bus_out = xtide_cpu_dout; end - else if (CGA_CRTC_OE) begin + else if (CGA_CRTC_OE_2) begin data_bus_out_from_chipset = 1'b1; - data_bus_out = CGA_CRTC_DOUT; + data_bus_out = CGA_CRTC_DOUT_2; end - else if (MDA_CRTC_OE) begin + else if (MDA_CRTC_OE_2) begin data_bus_out_from_chipset = 1'b1; - data_bus_out = MDA_CRTC_DOUT; + data_bus_out = MDA_CRTC_DOUT_2; end else if ((~opl_chip_select_n) && (~io_read_n)) begin data_bus_out_from_chipset = 1'b1; diff --git a/rtl/pll.qip b/rtl/pll.qip index 0f76722..8ecef1e 100644 --- a/rtl/pll.qip +++ b/rtl/pll.qip @@ -37,8 +37,8 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::NQ==::TnVtYmVyIE9mIENsb2Nrcw==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::NQ==::bnVtYmVyX29mX2Nsb2Nrcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Ng==::TnVtYmVyIE9mIENsb2Nrcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Ng==::bnVtYmVyX29mX2Nsb2Nrcw==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" @@ -103,11 +103,11 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::NTAuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MzI=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MzI=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ=" @@ -273,7 +273,7 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::My41Nzk0MTggTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ=" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::NTAuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=" @@ -362,12 +362,12 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNA==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNA==::ZmFsc2U=::Y19jbnRfYnlwYXNzX2VuNA==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNA==::dHJ1ZQ==::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNA==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2NQ==::MQ==::Y19jbnRfaGlfZGl2NQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2NQ==::MQ==::Y19jbnRfbG9fZGl2NQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2NQ==::MTY=::Y19jbnRfaGlfZGl2NQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2NQ==::MTY=::Y19jbnRfbG9fZGl2NQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDU=::MQ==::Y19jbnRfcHJzdDU=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q1::MA==::Y19jbnRfcGhfbXV4X3Byc3Q1" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNQ==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNQ==::ZmFsc2U=::Y19jbnRfYnlwYXNzX2VuNQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNQ==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Ng==::MQ==::Y19jbnRfaGlfZGl2Ng==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Ng==::MQ==::Y19jbnRfbG9fZGl2Ng==" @@ -463,8 +463,8 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX2ZiY2xrX211eF8y::bV9jbnQ=::cGxsX2ZiY2xrX211eF8y" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX21fY250X2luX3NyYw==::cGhfbXV4X2Nsaw==::cGxsX21fY250X2luX3NyYw==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3NsZl9yc3Q=::dHJ1ZQ==::cGxsX3NsZl9yc3Q=" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTQgSGkgRGl2aWRlLEMtQ291bnRlci00IExvdyBEaXZpZGUsQy1Db3VudGVyLTQgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci00IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTQgSW5wdXQgU291cmNlLEMtQ291bnRlci00IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTQgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MTYsMTYsMjU2LDI1NixmYWxzZSx0cnVlLGZhbHNlLGZhbHNlLDgsOCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxNCwxNCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwyOCwyOCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSw1NSw1NCwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDIyNCwyMjMsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwxLDIwLDQwMDAsMTYwMC4wIE1IeiwxLG5vbmUsZ2xiLG1fY250LHBoX211eF9jbGssdHJ1ZQ==::UGFyYW1ldGVyIFZhbHVlcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTQgSGkgRGl2aWRlLEMtQ291bnRlci00IExvdyBEaXZpZGUsQy1Db3VudGVyLTQgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci00IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTQgSW5wdXQgU291cmNlLEMtQ291bnRlci00IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTQgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTUgSGkgRGl2aWRlLEMtQ291bnRlci01IExvdyBEaXZpZGUsQy1Db3VudGVyLTUgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci01IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTUgSW5wdXQgU291cmNlLEMtQ291bnRlci01IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTUgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MTYsMTYsMjU2LDI1NixmYWxzZSx0cnVlLGZhbHNlLGZhbHNlLDgsOCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxNCwxNCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwyOCwyOCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSw1NSw1NCwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDIyNCwyMjMsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwxNiwxNiwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxLDIwLDQwMDAsMTYwMC4wIE1IeiwxLG5vbmUsZ2xiLG1fY250LHBoX211eF9jbGssdHJ1ZQ==::UGFyYW1ldGVyIFZhbHVlcw==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" diff --git a/rtl/pll.v b/rtl/pll.v index 6d387cd..ce685c0 100644 --- a/rtl/pll.v +++ b/rtl/pll.v @@ -13,6 +13,7 @@ module pll ( output wire outclk_2, // outclk2.clk output wire outclk_3, // outclk3.clk output wire outclk_4, // outclk4.clk + output wire outclk_5, // outclk5.clk output wire locked, // locked.export input wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll output wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll @@ -26,6 +27,7 @@ module pll ( .outclk_2 (outclk_2), // outclk2.clk .outclk_3 (outclk_3), // outclk3.clk .outclk_4 (outclk_4), // outclk4.clk + .outclk_5 (outclk_5), // outclk5.clk .locked (locked), // locked.export .reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll .reconfig_from_pll (reconfig_from_pll) // reconfig_from_pll.reconfig_from_pll @@ -73,7 +75,7 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: @@ -123,7 +125,7 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: diff --git a/rtl/pll/pll_0002.v b/rtl/pll/pll_0002.v index 6a4fd2c..fbf6d4a 100644 --- a/rtl/pll/pll_0002.v +++ b/rtl/pll/pll_0002.v @@ -22,6 +22,9 @@ module pll_0002( // interface 'outclk4' output wire outclk_4, + // interface 'outclk5' + output wire outclk_5, + // interface 'locked' output wire locked, @@ -38,7 +41,7 @@ module pll_0002( .pll_fractional_cout(32), .pll_dsm_out_sel("1st_order"), .operation_mode("direct"), - .number_of_clocks(5), + .number_of_clocks(6), .output_clock_frequency0("100.000000 MHz"), .phase_shift0("0 ps"), .duty_cycle0(50), @@ -54,7 +57,7 @@ module pll_0002( .output_clock_frequency4("3.579418 MHz"), .phase_shift4("0 ps"), .duty_cycle4(50), - .output_clock_frequency5("0 MHz"), + .output_clock_frequency5("50.000000 MHz"), .phase_shift5("0 ps"), .duty_cycle5(50), .output_clock_frequency6("0 MHz"), @@ -138,12 +141,12 @@ module pll_0002( .c_cnt_in_src4("ph_mux_clk"), .c_cnt_bypass_en4("false"), .c_cnt_odd_div_duty_en4("true"), - .c_cnt_hi_div5(1), - .c_cnt_lo_div5(1), + .c_cnt_hi_div5(16), + .c_cnt_lo_div5(16), .c_cnt_prst5(1), .c_cnt_ph_mux_prst5(0), .c_cnt_in_src5("ph_mux_clk"), - .c_cnt_bypass_en5("true"), + .c_cnt_bypass_en5("false"), .c_cnt_odd_div_duty_en5("false"), .c_cnt_hi_div6(1), .c_cnt_lo_div6(1), @@ -241,7 +244,7 @@ module pll_0002( .pll_slf_rst("true") ) altera_pll_i ( .rst (rst), - .outclk ({outclk_4, outclk_3, outclk_2, outclk_1, outclk_0}), + .outclk ({outclk_5, outclk_4, outclk_3, outclk_2, outclk_1, outclk_0}), .locked (locked), .reconfig_to_pll (reconfig_to_pll), .fboutclk ( ),