From 2f55052d2ee15902f5e6154c357325dcbdd8faf2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Aitor=20G=C3=B3mez?= Date: Fri, 11 Nov 2022 09:06:17 +0100 Subject: [PATCH] Change mouse port to COM1 For the time being, the COM2 port is deleted. --- rtl/KFPC-XT/HDL/Chipset.sv | 30 ++++++----- rtl/KFPC-XT/HDL/Peripherals.sv | 91 +++++++++++++++++----------------- 2 files changed, 60 insertions(+), 61 deletions(-) diff --git a/rtl/KFPC-XT/HDL/Chipset.sv b/rtl/KFPC-XT/HDL/Chipset.sv index 4667099..1a49967 100644 --- a/rtl/KFPC-XT/HDL/Chipset.sv +++ b/rtl/KFPC-XT/HDL/Chipset.sv @@ -99,14 +99,13 @@ module CHIPSET ( output logic tandy_16_gfx, // UART input logic clk_uart, - input logic clk_uart2, - input logic uart_rx, - output logic uart_tx, - input logic uart_cts_n, - input logic uart_dcd_n, - input logic uart_dsr_n, - output logic uart_rts_n, - output logic uart_dtr_n, + input logic uart2_rx, + output logic uart2_tx, + input logic uart2_cts_n, + input logic uart2_dcd_n, + input logic uart2_dsr_n, + output logic uart2_rts_n, + output logic uart2_dtr_n, // SDRAM input logic enable_sdram, output logic initilized_sdram, @@ -258,7 +257,6 @@ module CHIPSET ( .clk_sys (clk_sys), .cpu_clock (cpu_clock), .clk_uart (clk_uart), - .clk_uart2 (clk_uart2), .peripheral_clock (peripheral_clock), .turbo_mode (turbo_mode), .reset (reset), @@ -323,13 +321,13 @@ module CHIPSET ( .tandy_snd_e (tandy_snd_e), .tandy_snd_rdy (tandy_snd_rdy), .tandy_16_gfx (tandy_16_gfx), - .uart_rx (uart_rx), - .uart_tx (uart_tx), - .uart_cts_n (uart_cts_n), - .uart_dcd_n (uart_dcd_n), - .uart_dsr_n (uart_dsr_n), - .uart_rts_n (uart_rts_n), - .uart_dtr_n (uart_dtr_n), + .uart2_rx (uart2_rx), + .uart2_tx (uart2_tx), + .uart2_cts_n (uart2_cts_n), + .uart2_dcd_n (uart2_dcd_n), + .uart2_dsr_n (uart2_dsr_n), + .uart2_rts_n (uart2_rts_n), + .uart2_dtr_n (uart2_dtr_n), .ems_enabled (ems_enabled), .ems_address (ems_address), .map_ems (map_ems), diff --git a/rtl/KFPC-XT/HDL/Peripherals.sv b/rtl/KFPC-XT/HDL/Peripherals.sv index 62472bf..07c5bdc 100644 --- a/rtl/KFPC-XT/HDL/Peripherals.sv +++ b/rtl/KFPC-XT/HDL/Peripherals.sv @@ -82,14 +82,13 @@ module PERIPHERALS #( output logic tandy_16_gfx, // UART input logic clk_uart, - input logic clk_uart2, - input logic uart_rx, - output logic uart_tx, - input logic uart_cts_n, - input logic uart_dcd_n, - input logic uart_dsr_n, - output logic uart_rts_n, - output logic uart_dtr_n, + input logic uart2_rx, + output logic uart2_tx, + input logic uart2_cts_n, + input logic uart2_dcd_n, + input logic uart2_dsr_n, + output logic uart2_rts_n, + output logic uart2_dtr_n, // EMS input logic ems_enabled, input logic [1:0] ems_address, @@ -194,7 +193,7 @@ module PERIPHERALS #( wire cga_chip_select_n = ~(~iorq && ~address_enable_n && enable_cga & (address[19:15] == 5'b10111)); // B8000 - BFFFF (16 KB / 32 KB) wire mda_chip_select_n = ~(~iorq && ~address_enable_n && enable_mda & (address[19:15] == 6'b10110)); // B0000 - B7FFF (8 repeated blocks of 4Kb) wire uart_cs = (~address_enable_n && {address[15:3], 3'd0} == 16'h03F8); - wire uart2_cs = (~address_enable_n && {address[15:3], 3'd0} == 16'h02F8); +// wire uart2_cs = (~address_enable_n && {address[15:3], 3'd0} == 16'h02F8); wire lpt_cs = (iorq && ~address_enable_n && address[15:0] == 16'h0378); wire tandy_page_cs = (iorq && ~address_enable_n && address[15:0] == 16'h03DF); wire xtctl_cs = (iorq && ~address_enable_n && address[15:0] == 16'h8888); @@ -265,7 +264,7 @@ module PERIPHERALS #( logic keybord_interrupt; logic uart_interrupt; logic fdd_interrupt; - logic uart2_interrupt; + //logic uart2_interrupt; logic [7:0] interrupt_data_bus_out; KF8259 u_KF8259 @@ -293,7 +292,7 @@ module PERIPHERALS #( fdd_interrupt, interrupt_request[5], uart_interrupt, - uart2_interrupt, + interrupt_request[3], // uart2_interrupt interrupt_request[2], keybord_interrupt, timer_interrupt}) @@ -400,7 +399,7 @@ module PERIPHERALS #( logic ps2_send_clock; logic keybord_irq; logic uart_irq; - logic uart2_irq; + //logic uart2_irq; logic [7:0] keycode; logic [7:0] tandy_keycode; logic prev_ps2_reset; @@ -508,7 +507,7 @@ module PERIPHERALS #( logic keybord_interrupt_ff; logic uart_interrupt_ff; - logic uart2_interrupt_ff; + //logic uart2_interrupt_ff; always_ff @(posedge clock, posedge reset) begin if (reset) @@ -517,8 +516,8 @@ module PERIPHERALS #( keybord_interrupt <= 1'b0; uart_interrupt_ff <= 1'b0; uart_interrupt <= 1'b0; - uart2_interrupt_ff <= 1'b0; - uart2_interrupt <= 1'b0; + //uart2_interrupt_ff <= 1'b0; + //uart2_interrupt <= 1'b0; end else begin @@ -526,19 +525,19 @@ module PERIPHERALS #( keybord_interrupt <= keybord_interrupt_ff; uart_interrupt_ff <= uart_irq; uart_interrupt <= uart_interrupt_ff; - uart2_interrupt_ff <= uart2_irq; - uart2_interrupt <= uart2_interrupt_ff; + //uart2_interrupt_ff <= uart2_irq; + //uart2_interrupt <= uart2_interrupt_ff; end end logic prev_io_read_n; logic prev_io_write_n; logic [7:0] write_to_uart; - logic [7:0] write_to_uart2; + //logic [7:0] write_to_uart2; logic [7:0] uart_readdata_1; logic [7:0] uart_readdata; - logic [7:0] uart2_readdata_1; - logic [7:0] uart2_readdata; + //logic [7:0] uart2_readdata_1; + //logic [7:0] uart2_readdata; always_ff @(posedge clock) begin @@ -572,12 +571,12 @@ module PERIPHERALS #( if (~io_write_n) begin write_to_uart <= internal_data_bus; - write_to_uart2 <= internal_data_bus; + //write_to_uart2 <= internal_data_bus; end else begin write_to_uart <= write_to_uart; - write_to_uart2 <= write_to_uart2; + //write_to_uart2 <= write_to_uart2; end if ((lpt_cs) && (~io_write_n)) @@ -596,6 +595,9 @@ module PERIPHERALS #( end wire iorq_uart = (io_write_n & ~prev_io_write_n) || (~io_read_n & prev_io_read_n); + wire uart_tx; + wire rts_n; + uart uart1 ( .clk (clock), @@ -608,26 +610,20 @@ module PERIPHERALS #( .write (io_write_n & ~prev_io_write_n), .readdata (uart_readdata_1), .cs (uart_cs & iorq_uart), - - .rx (uart_rx), - .tx (uart_tx), - .cts_n (uart_cts_n), - .dcd_n (uart_dcd_n), - .dsr_n (uart_dsr_n), - .rts_n (uart_rts_n), - .dtr_n (uart_dtr_n), + .rx (uart_tx), + .cts_n (0), + .dcd_n (0), + .dsr_n (0), .ri_n (1), - + .rts_n (rts_n), .irq (uart_irq) ); - - wire uart2_tx; - wire rts_n; - + + /* uart uart2 ( .clk (clock), - .br_clk (clk_uart2), + .br_clk (clk_uart), .reset (reset), .address (address[2:0]), @@ -636,15 +632,20 @@ module PERIPHERALS #( .write (io_write_n & ~prev_io_write_n), .readdata (uart2_readdata_1), .cs (uart2_cs & iorq_uart), - .rx (uart2_tx), - .cts_n (0), - .dcd_n (0), - .dsr_n (0), + + .rx (uart2_rx), + .tx (uart2_tx), + .cts_n (uart2_cts_n), + .dcd_n (uart2_dcd_n), + .dsr_n (uart2_dsr_n), + .rts_n (uart2_rts_n), + .dtr_n (uart2_dtr_n), .ri_n (1), - .rts_n (rts_n), + .irq (uart2_irq) ); - + */ + MSMouseWrapper MSMouseWrapper_inst ( .clk(clock), @@ -653,7 +654,7 @@ module PERIPHERALS #( .ps2dta_out(ps2_mousedat_out), .ps2clk_out(ps2_mouseclk_out), .rts(~rts_n), - .rd(uart2_tx) + .rd(uart_tx) ); // Timing of the readings may need to be reviewed. @@ -662,12 +663,12 @@ module PERIPHERALS #( if (~io_read_n) begin uart_readdata <= uart_readdata_1; - uart2_readdata <= uart2_readdata_1; + //uart2_readdata <= uart2_readdata_1; end else begin uart_readdata <= uart_readdata; - uart2_readdata <= uart2_readdata; + //uart2_readdata <= uart2_readdata; end end